Webinars 

How Reliable is Your FPGA Design? Tips and Tricks for Building-in High Reliability
Learn how to automatically "build in" high reliability using Synopsys Synplify Premier FPGA design tool.
Sharath Duraiswami, Senior Corporate Applications Engineer, Synopsys
Oct 02, 2014
 
ProtoCompiler Accelerates HAPS FPGA-Based Prototyping Systems
This webcast examines the latest generation of design tools for prototyping, Synopsys ProtoCompiler, a suite of design automation and debugging tools for the Synopsys HAPS Series of FPGA-based prototypes.
Troy Scott, Product Marketing Manager, Synopsys
Jul 23, 2014
 
Automate ASIC to FPGA-based Prototype Conversion with Synplify
Using Synplify, automate ASIC to FPGA-based prototype conversion to accelerate fast FPGA-based working prototype bring-up, debug and validation.
Dr. Angela Sutton, Staff Product Marketing Manager, FPGA Implementation, Synopsys
Jun 18, 2014
 
How to Accelerate the Development of ARMv8 Based Server
Learn about tools and methods for early bring-up and debug of software stacks for ARMv8-based SoCs and servers.
Achim Nohl, Technical Marketing Manager, Synopsys; Marc Serughetti, Director of Business Development, Synopsys
Jun 10, 2014
 
Performance Analysis and Optimization of ARM® CoreLink™ NIC-400 based Systems
A case study demonstration of system-level performance analysis and optimization.
William Orme, Strategic Marketing Manager, Interconnect products, ARM; Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys
May 20, 2014
 
Increase FPGA Performance with Enhanced Capabilities of Synplify Pro and Premier
Timing is everything! Find out how to reproducibly improve FPGA performance results using Synplify Pro and Synplify Premier. This webinar includes tips on how to set up you FPGA design to achieve better timing results downstream, recommended techniques to analyze and tune design performance for faster timing closure and new "under the hood" Synplify Premier placement-aware logic synthesis technology that further boosts timing performance.
Paul Owens, Senior CAE, Synplify Business Group, Synopsys
May 06, 2014
 
Streamlining IP and Subsystem Prototyping with HAPS-DX
In this webinar we will introduce the new HAPS Developer eXpress (HAPS-DX) solution for complex IP and subsystem prototyping to accelerate IP and subsystem bring-up and streamline IP to SoC integration.
Neil Songcuan, Senior Product Marketing Manager, Synopsys
Jan 29, 2014
 
LTE and LTE-A MIMO Link Adaption Performance Optimization
Learn the link adaptation methods in LTE/LTE-A and present strategies for simulating and designing receivers to implement these methods.
John Lundell, R&D Manager, Synopsys
Dec 10, 2013
 
Optimize Your Micro-server SoC Architecture for Power and Performance
In this session we will address the architecture design challenges associated with HW-SW partitioning.
Patrick Sheridan and Tim Kogel, Synopsys
Oct 10, 2013
 
Debug and Bring-Up Automation for the HAPS-70 Series FPGA-Based Prototyping System
This webcast explores debug and bring-up automation features unique to the next-generation FPGA-based prototyping system, the Synopsys HAPS-70 Series.
Nathan Henderson, Corporate Applications Engineering Manager, Synopsys
Sep 26, 2013
 
Using FPGA-based Prototyping to Validate IP Integration Without Breaking a Sweat
Learn how to test DesignWare USB 3.0 interface IP and implement it on a HAPS FPGA-based Prototyping System. Review best practices on how to utilize Synopsys' Identify HW/SW tools to test the interface in the context of the larger chip design.
John Kuhns, Synopsys Professional Services, Senior Design Consultant
Jul 17, 2013
 
Conquering HSPA+ Modem Design
To understand the design flow and provide an introduction to InterDigital’s HSPA+ modem IP.
William Lawton, Senior Manager, InterDigital Communications; Vafa Ghazi-Moghadam, Staff R&D Engineer, Synopsys
May 15, 2013
 
Case Study: Design and FPGA-Prototyping of an Application Specific Processor for Embedded Vision
This webinar introduces Synopsys’ Vision Processor Design and Prototyping solution, featuring Processor Designer and HAPS FPGA-prototyping.
Drew Taussig, Corporate Applications Engineer, Synopsys
May 07, 2013
 
Optimizing and Validating the Performance of Your AMBA®4 Interconnect
Learn how to use Synopsys Platform Architect to drive performance criteria that can now be verified in the functional verification process through tight integration with Synopsys Verification IP.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys
Apr 25, 2013
 
Synopsys Vision Processor Starter Kit: Implementing Embedded Vision Applications Optimized for Power
This webinar introduces the new Vision Processor Starter Kit from Synopsys, featuring Processor Designer, the industry’s leading ASIP design tool.
Bo Wu, Technical Marketing Manager, Synopsys
Jan 16, 2013
 
LTE-Advanced Modems Coming to Life
This webinar will explain the steps that need to be taken at the different stages of the design process, and how these steps can be integrated into a complete design and verification flow.
Dr. Vafa Ghazi-Moghadam, R&D Engineer, Synopsys; Simon Ache, Product Manager, Rohde&Schwarz
Nov 08, 2012
 
LTE-A Physical Layer Design & Simulation
Learn about the LTE-Advanced standard (3GPP Rel.10), its main enhancements over LTE Rel.8 and their impact on the overall system performance.
Dr. Vafa Ghazi-Moghadam, Staff R&D Engineer, Synopsys Inc.
Mar 08, 2012
 
LTE Physical Layer Design: Basics
Overview of the LTE standard, LTE simulation library and Synopsys SPW algorithm design tool.
Bo Wu, Technical Marketing Manager, Synopsys
Sep 15, 2010
 
LTE Physical Layer Design: Optimization
Learn more about LTE physical layer design and how design choices can impact implementation and performance.
John Lundell, R&D Manager, Synopsys
Aug 18, 2010
 
LTE Physical Layer Design: Synchronization
Learn more about some of the features of the LTE User Equipment (UE) acquisition and synchronization process.
Louie Valena, Corporate Applications Engineer, Synopsys
Jul 21, 2010
 
Using Simulation to Implement a Robust Design Flow
Listen to our Robust Design Web Seminar to discover how Robust Design methodologies coupled with Synopsys' Saber simulation and analysis solution can improve your design performance and reliability for mechatronic systems.
Mike Jensen, Corporate Applications Engineer, Synopsys
Dec 10, 2006
 


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