White Papers 

IC Compiler II Multi-Level Physical Hierarchy Floorplanning
Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a given time resulting in longer layout schedules that are risky at best. This paper presents the need for multi-level physical hierarchy floorplanning, the challenges inherent with this style when using tools limited to two levels of hierarchy, and discusses how IC Compiler II addresses these challenges.
Steve Kister, Technical Marketing Manager, Synopsys

IC Validator and In-Design Metal Fill in IC Compiler II
Metal fill has evolved from an afterthought performed by the foundries to a mission critical design requirement that customers now carefully design themselves in order to achieve high yield and maximum design timing performance. IC Validator and In-Design metal fill in IC Compiler II is architected to be the ideal comprehensive unified fill solution at 20-nm and below.
Harvey Toyama, Product Marketing, Manager, Synopsys

Concurrent Clock and Data Optimization with IC Compiler II
To advance concurrent clock and data optimization, we need to go beyond incremental enhancements and bolt-on solutions. An optimal solution to CCD needs to provide a fast, convergent, multi objective driven engine that is native to all stages of place and route, and supports all clocking styles. IC Compiler II has been architected with the objective of driving CCD into the future.
Geetha Rangarajan, Technical Marketing Manager, Synopsys

IC Compiler II: 5X Faster Closure on Advanced Designs With Complex MCMM
IC Compiler II with its native support for MCMM and MV is the most comprehensive, physical implementation system for advanced designs. It delivers 5X faster throughput, 3X larger capacities, and helps achieve the best QoR with complex MCMM requirements. It’s also easy to use.
Jafar Safdar, Product Marketing Manager, Synopsys

IC Compiler II: Finding the Best Floorplan, Fast
Today’s designs are large and very complex, requiring hierarchical planning and implementation methodologies. A fast, accurate solution enables design teams to converge on the best solution more quickly within the time scheduled for floor plan exploration. IC Compiler II provides a solution that enables designers to find the best floor plan for implementation, quickly.
Steve Kister, Technical Marketing Manager, Synopsys, Inc

Accelerated Optimization with IC Compiler II
Efficient optimization is a necessary yet challenging aspect of the physical implementation flow. Newer nodes and growing designs are all conspiring to place growing demands on this already difficult area of efficient IC design. IC Compiler II and the underlying physical optimization engines have been re-thought and re-architected to address these growing challenges and to set the stage for the future.
Charles Hsiao, Staff CAE, Synopsys

IC Compiler II: Building a Scalable Platform to Enable the Next 10x in Physical Design
Keeping up with the pace demanded by Moore’s law is putting increasingly expanding strains on today’s design planning and physical implementation tools. Merely tweaking existing solutions will not provide a path to handle the complex designs that we are quickly moving towards. IC Compiler II’s development has embraced the opportunity to rethink the implementation and data management paradigm to deliver on leading capacity and throughput.
Haimin Hua, CAE Manager, Synopsys

Fast, Convergent Clock Synthesis & Optimization with IC Compiler II
As more and more challenges from capacity, variability and complexity need to be managed, it is imperative to readdress and rethink both the algorithmic and infrastructural aspects of clock implementation. IC Compiler II has been architected with all of these challenges in mind and delivers a clocking solution with a breadth of technologies to meet the needs of today’s and tomorrow’s clock design challenges.
Kalaivani Singaram, CAE Sr. Manager, Synopsys

Advanced Design Planning in IC Compiler II
Design exploration and planning is becoming an increasingly critical step of the design creation process as growing constraints and requirements are placed upon it. IC Compiler II has been architected from the ground up with the express focus to address the three key challenges of design planning.
Rajiv Dave, CAE Manager, Synopsys

Realizing Advanced P&R Design Utilizing Established Process Nodes
Despite the high mindshare garnered by the latest developments at 16nm and 10nm, the fact is that the majority of designs taped out today are at 45nm and above. It is clearly the time to disassociate the term "advanced" from "technology node". Advanced designs are occurring at both established process nodes and at emerging process nodes. Today, advanced design should be considered process node independent. This paper takes an i-ndepth look at advanced place and route design using established process nodes.
Harvey Toyama, Synopsys

Accelerating 20nm Double Patterning Verification
This whitepaper presents the key concepts of DPT compliant design and demonstrates how new signoff technology in IC Validator makes it possible to ensure 20nm manufacturing compliance. Recognizing that the designer productivity necessary cannot be achieved alone by point-tool enhancements and post-processing techniques, the paper outlines advances in In-Design physical verification within IC Compiler.
Paul Friedberg, CAE, Synopsys; Stelios Diamantidis, Product Marketing, Synopsys

Physical Verification of FinFETs and Fully Depleted SOI
It has come to be broadly accepted in the semiconductor industry that short-channel effects severely limit bulk planar transistor performance, and alternative device structures will necessarily have to be adopted if we are to shrink process geometries below 20nm. This paper explores the two major contenders for the new transistor architecture: finFETs and fully depleted silicon-on-insulator.
Ron Duncan, Applications Engineering Manager, Synopsys; Marc Swinnen, Product Marketing Manager, Synopsys

Multi-Source CTS Delivers Flexible High Performance and Variation Tolerance
Multi-Source CTS delivers the ideal hybrid solution for designers seeking the best of conventional CTS and pure clock mesh. IC Compiler Multi-Source CTS provides better high-speed performance and OCV tolerance than conventional CTS and is more tolerant of complex floorplans and provides more flexibility for clock gating depth than pure clock mesh.
Harvey Toyama, Synopsys Implementation Group

IC Validator: Physical Verification for Analog Designs
Physical verification challenges of analog designs are different than the challenges of large digital designs. In addition to complex runset requirements, a tight interface to a parasitic extraction tool and an easy-to-use GUI are needed to use a runset effectively in an analog design environment. IC Validator, the latest generation physical verification tool, can be used to solve these issues. This paper addresses many of the physical verification requirements of analog designers and how they are met with IC Validator.
Al Blais, Global Technology Services

Physical Datapath - Improved Productivity for All Designs
Currently, most EDA tools do not provide a solution that addresses the limitations of a custom datapath flow. This paper discusses datapath designs, benefits, limitations, and the use of an automated datapath design capability that allows both custom and ASIC designers to meet aggressive design objectives with ever-tighter project deadlines.
Jafar Safdar, Synopsys Implementation Group

Multicorner-Multimode – A Necessary and Manageable Reality of Design
Resolving correlation issues is a time consuming step and is all the more challenging when it has to be done across multiple corners and modes. Tight correlation to signoff is critical for faster time to results. d d
Ashwini Mulgaonkar, Synopsys Implementation Group

IC Validator: GDS Merge
With today’s increasingly complicated design flows, creating a snapshot of a design’s full mask set to run physical verification at intermediate points during the design cycle, or in-design, presents many challenges. This paper presents an optimal approach to creating a working snapshot of a design’s complete mask data set for the purposes of in-design physical verification with IC Validator, Synopsys’ award-winning physical verification platform for advanced nodes.
Rich Santilli, Staff CAE

Minimizing Time to Complete a Hierarchical Design
This paper addresses design exploration and planning in a hierarchical flow for larger SoCs and discusses techniques for achieving predictable design convergence without surprises.
Steve Kister, Technical Marketing Manager

IC Validator: Automatic DRC Repair
This paper presents how in-design physical verification with IC Validator enables Automatic DRC Repair (ADR), a novel capability that makes it possible for designers to automatically detect, repair and revalidate signoff DRC violations with negligible physical or timing impact, all within IC Compiler.
Paul Friedberg, Staff CAE

Realizing Low Power IC Design: It Starts with the Clock Tree
There are numerous techniques to achieve a low-power design and several approaches to structuring the flow. As a starting point, high performance designs require a benchmark proven low-skew, low-insertion delay CTS solution. Correlation to industry standard sign-off engines for accuracy and minimum data format translations are required to achieve fast design closure. The optimal solution includes complete low power capability throughout the design flow. This paper addresses low power design issues and includes technologies and techniques to achieve high performance, low power design goals.
Harvey Toyama, Synopsys Implementation Group

Advanced Design Challenges Make DFM-Friendly Routing A Must-Have
Timing, area, power, and signal integrity have traditionally been the primary objectives of design technology, and the primary care-abouts for designers and CAD engineers. Increasingly manufacturability and yield have also become critical design objectives, and multiple design-for-manufacturability (DFM) optimization techniques have been added to the design flows. As manufacturability has been a secondary goal, conventional routers have been optimizing for it after timing optimization – the point at which all of the primary design goals have already been met. While this methodology has worked well up to the 65nm technology node, it starts to break down at 45nm and below. This paper talks about the routing challenges at 45nm and below and the need for modern DFM-friendly routing technologies for achieving better manufacturability and higher yield without sacrificing performance.
Maria Gkatziani, Synopsys Implementation Group

Accelerating Physical Verification with an In-Design Flow
There is a growing need for a concurrent physical design and physical verification flow, also known as an in-design physical verification flow. This flow improves the overall turnaround time and ease of use of the physical verification process. This paper provides a production-proven example of this flow.
Elango Velayutham

Clock Mesh for Mainstream Designs
By its very nature, even the best conventional clock tree synthesis leaves both performance and variation tolerance potential on the table. Clock mesh offers the designer a means of achieving extreme high performance along with the avoidance of process variation effects. Long known as the clock distribution method for high-end microprocessors, clock mesh also offers significant variation tolerance. Clock mesh use to be an entirely manual, difficult to analyze technology, but new advances in clock mesh automation and analysis now enable it to be considered as a mainstream clock distribution solution.
Harvey Toyama, Synopsys Implementation Group

Achieving Faster Time-to-Tapeout with In-Design Sign-Off Metal Fill
Achieving correct-by-construction results during implementation significantly reduces time to tapeout and avoids schedule delays. This paper presents a pushbutton flow to generate timing-aware, signoff quality metal fill during place and route.
David Pemberton-Smith

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