IC Validator 

IC Validator is a complete physical verification tool, performing the increasingly complex DRC and LVS sign-off checks. In addition, it has been specifically architected for In-Design physical verification. In-Design physical verification means that the Place and Route engineers can run DRC and practical DFM steps alongside place and route within the familiar IC Compiler physical design environment.

The three cornerstones of IC Validator are
  • High performance to run compute-intensive checks and DFM utilities, such as metal fills
  • Foundry qualification for final signoff for DRC and LVS
  • Seamless integration with Synopsys’ leading Place and Route solution, IC Compiler
In-Design physical verification with IC Validator and IC Compiler delivers 100 tapeouts just one year after introduction.

In this video, Synopsys Chairman and CEO, Dr. Aart de Geus shares his view on the broad and rapid adoption of this new technology and how it could change physical verification going forward.

Antun Domic Introduces IC Validator

IC Validator is a full, sign-off quality verification tool that delivers the highest performance to enable significantly improved time-to-tapeout with better DFM closure. Hear what Antun Domic, senior vice president and general manager of Synopsys' Implementation Group, has to say about this new physical verification solution.

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