|IC Compiler II Multi-Level Physical Hierarchy Floorplanning|
Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a given time resulting in longer layout schedules that are risky at best. This paper presents the need for multi-level physical hierarchy floorplanning, the challenges inherent with this style when using tools limited to two levels of hierarchy, and discusses how IC Compiler II addresses these challenges.
Steve Kister, Technical Marketing Manager, Synopsys
|IC Validator and In-Design Metal Fill in IC Compiler II|
Metal fill has evolved from an afterthought performed by the foundries to a mission critical design requirement that customers now carefully design themselves in order to achieve high yield and maximum design timing performance. IC Validator and In-Design metal fill in IC Compiler II is architected to be the ideal comprehensive unified fill solution at 20-nm and below.
Harvey Toyama, Product Marketing, Manager, Synopsys
| IC Compiler II: Finding the Best Floorplan, Fast|
Today’s designs are large and very complex, requiring hierarchical planning and implementation methodologies. A fast, accurate solution enables design teams to converge on the best solution more quickly within the time scheduled for floor plan exploration. IC Compiler II provides a solution that enables designers to find the best floor plan for implementation, quickly.
Steve Kister, Technical Marketing Manager, Synopsys, Inc
|FinFET Technology – Understanding and Productizing a New Transistor From TSMC and Synopsys|
This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with
Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this solution include
comprehensive FinFET profiling without impact to design tool runtime and proven, verified IP availability. The
TSMC 16-nm FinFET solution will ensure mutual customers swiftly move to building the next generation SoCs.
Jason S.T. Chen, TSMC; Andy Biddle, Synopsys
|Realizing Advanced P&R Design Utilizing Established Process Nodes|
Despite the high mindshare garnered by the latest developments at 16nm and 10nm, the fact is that the
majority of designs taped out today are at 45nm and above. It is clearly the time to disassociate the term "advanced" from "technology node". Advanced designs are occurring at both established process nodes and at emerging process nodes. Today, advanced design should be considered process node independent. This paper takes an i-ndepth look at advanced place and route design using established process nodes.
Harvey Toyama, Synopsys
|Physical Verification of FinFETs and Fully Depleted SOI|
It has come to be broadly accepted in the semiconductor industry that short-channel effects severely limit bulk planar transistor performance, and alternative device structures will necessarily have to be adopted if we are to shrink process geometries below 20nm. This paper explores the two major contenders for the new transistor architecture: finFETs and fully depleted silicon-on-insulator.
Ron Duncan, Applications Engineering Manager, Synopsys; Marc Swinnen, Product Marketing Manager, Synopsys
|Accelerated Layout for Analog/Mixed-Signal in Nanometer SoCs|
A much more accelerated approach for creating and integrating analog/mixed-signal functions in SoC designs is possible using automated methods to reduce the total effort needed, enable layout to proceed concurrently with circuit design, and typically produce more optimal layouts—especially for smaller die sizes.
Lyndon Lim, Synopsys
|IC Compiler: Multi-Source CTS|
Multi-source clock tree is a hybrid containing the best aspects of a conventional clock tree and a pure clock mesh. This paper illustrates the benefits such as lower skew and better on-chip-variation (OCV) performance compared to a conventional clock tree.
Harvey Toyama, Synopsys Implementation Group
|Custom and Mixed-Signal Design Solution|
Synopsys' unified solution for custom and cell-based design and verification provides a comprehensive, highly integrated suite of tools for advanced-node mixed-signal SoC design. The high degree of integration and interoperability shortens time-to-tapeout and improves design quality.
|Unified Implementation Solution for Digital and Custom SoC Designs|
The Galaxy Implementation Platform provides seamless integration between the IC Compiler physical implementation and Galaxy Custom Designer custom implementation solutions, accelerating the design development cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development while maintaining design data integrity.
|IC Validator: Automatic DRC Repair|
This paper presents how in-design physical verification with IC
Validator enables Automatic DRC Repair (ADR), a novel capability that makes it possible for designers to
automatically detect, repair and revalidate signoff DRC violations with negligible physical or timing impact, all within IC Compiler.
Paul Friedberg, Staff CAE
|IC Validator: GDS Merge|
With today’s increasingly complicated design flows, creating a snapshot of a design’s full mask set to run physical verification at intermediate points during the design cycle, or in-design, presents many challenges. This paper presents an optimal approach to creating a working snapshot of a design’s complete mask data set for the purposes of in-design physical verification with IC Validator, Synopsys’ award-winning physical verification platform for advanced nodes.
Rich Santilli, Staff CAE
|IC Validator: Physical Verification for Analog Designs|
Physical verification challenges of analog designs are different than the challenges of large digital designs. In addition to complex runset requirements, a tight interface to a parasitic extraction tool and an easy-to-use GUI are needed to use a runset effectively in an analog design environment. IC Validator, the latest generation physical verification tool, can be used to solve these issues. This paper addresses many of the physical verification requirements of analog designers and how they are met with IC Validator.
Al Blais, Global Technology Services
|Minimizing Time to Complete a Hierarchical Design|
This paper addresses design exploration and planning in a hierarchical flow for larger SoCs and discusses techniques for achieving predictable design convergence without surprises.
Steve Kister, Technical Marketing Manager
|SmartDRD Automated DRC Visualization and Correction|
SmartDRD is a new, innovative technology built into Galaxy Custom Designer™ Layout Editor (LE) for interactive DRC violation visualization, detection and correction, commonly known as design-rule-driven (DRD) editing
|Multicore and Distributed Processing With TetraMAX® ATPG|
Running automatic test pattern generation (ATPG) on a single processor may take a week or longer to complete, especially for very large designs and when testing at-speed fault models. Designers and test engineers need a straightforward way to reduce ATPG runtime by many factors and deliver working test patterns in days, not weeks.
Cy Hay, Product Manager
|Improve Design Productivity with Quality Checks on IP Timing Constraints|
When combining intellectual property (IP) blocks from various sources, the chip-level implementation teams may not have the detailed IP knowledge required to develop timing constraints for the IP.
Michael Robinson, Senior Design Consultant, Synopsys Professional Services
|Realizing Low Power IC Design: It Starts with the Clock Tree|
There are numerous techniques to achieve a low-power design and several approaches to structuring the flow. As a starting point, high performance designs require a benchmark proven low-skew, low-insertion delay CTS solution. Correlation to industry standard sign-off engines for accuracy and minimum data format translations are required to achieve fast design closure. The optimal solution includes complete low power capability throughout the design flow. This paper addresses low power design issues and includes technologies and techniques to achieve high performance, low power design goals.
Harvey Toyama, Synopsys Implementation Group
|Clock Mesh for Mainstream Designs|
By its very nature, even the best conventional clock tree synthesis leaves both performance and variation tolerance potential on the table. Clock mesh offers the designer a means of achieving extreme high performance along with the avoidance of process variation effects. Long known as the clock distribution method for high-end microprocessors, clock mesh also offers significant variation tolerance. Clock mesh use to be an entirely manual, difficult to analyze technology, but new advances in clock mesh automation and analysis now enable it to be considered as a mainstream clock distribution solution.
Harvey Toyama, Synopsys Implementation Group
|Advanced Design Challenges Make DFM-Friendly Routing A Must-Have |
Timing, area, power, and signal integrity have traditionally been the primary objectives of design technology, and the primary care-abouts for designers and CAD engineers. Increasingly manufacturability and yield have also become critical design objectives, and multiple design-for-manufacturability (DFM) optimization techniques have been added to the design flows. As manufacturability has been a secondary goal, conventional routers have been optimizing for it after timing optimization – the point at which all of the primary design goals have already been met. While this methodology has worked well up to the 65nm technology node, it starts to break down at 45nm and below. This paper talks about the routing challenges at 45nm and below and the need for modern DFM-friendly routing technologies for achieving better manufacturability and higher yield without sacrificing performance.
Maria Gkatziani, Synopsys Implementation Group
|Realizing a Scalable Hierarchical Design Flow: What’s Needed for Large Designs|
Today’s system on a chip (SoC) designs continue to get larger and more complex. Given that consumer products are now the main driver for SoC designs, design teams must deliver chips quickly to capture as much revenue as possible from the latest consumer trend. Flat implementation flows are inefficient in terms of computer system resource requirements and runtimes for large SoC designs. Teams are turning to hierarchical design flows to implement these designs. This paper discusses design exploration and planning in a hierarchical flow for large SoCs and delves into efficient techniques that produce fast turn times and a concurrent physical implementation that enables predictable design convergence.
Steve Kister, Synopsys Implementation Group
|Achieving Faster Time-to-Tapeout with In-Design Sign-Off Metal Fill |
Achieving correct-by-construction results during implementation significantly reduces time to tapeout and avoids schedule delays. This paper presents a pushbutton flow to generate timing-aware, signoff quality metal fill during place and route.
|Accelerating Physical Verification with an In-Design Flow|
There is a growing need for a concurrent physical design and physical verification flow, also known as an in-design physical verification flow. This flow improves the overall turnaround time and ease of use of the physical verification process. This paper provides a production-proven example of this flow.