Signoff users have a few key requirements for their signoff tool of choice, runtime and capacity to handle their largest chip size requirements, efficient multi-scenario analysis to verify timing across all corners and modes, margin control to reduce over-design and maximize chip performance, and accuracy to ensure correlation to silicon. The Synopsys PrimeTime® Suite addresses these requirements by delivering fast, memory-efficient scalar and multicore computing, distributed multi-scenario analysis and ECO guidance, using variation-aware Composite Current Source (CCS) modeling that extends static timing analysis to include Crosstalk Timing, Noise, Power and constraint analysis.
The Synopsys PrimeTime suite, including PrimeTime, PrimeTime SI, PrimeTime ADV, PrimeTime PX and PrimeTime GCA, provides a single, golden, trusted signoff solution for timing, signal integrity, power, timing constraint and variation-aware analysis. It delivers HSPICE® accurate signoff analysis that helps pinpoint problems prior to tapeout thereby reducing risk, ensuring design integrity, and lowering the cost of design. This industry gold-standard solution improves your team’s productivity by delivering fast turnaround on development schedules for large and small designs while ensuring firstpass silicon success through greater predictability and the highest accuracy.
Figure 1: Galaxy Platform Signoff Solutions
HSPICE-Accurate Results Minimize Over-Design
HSPICE-accurate analysis pinpoints timing problems quickly and reduces ECO fixing time. Use of CCS models provides consistent results for static timing, signal integrity, power, and variation-aware analysis. Path-based analysis is available to zero in on your most challenging timing paths. Advanced on-chip variation modeling and variation-aware analysis deliver additional margin control. This helps designers avoid the over- and under-design of chips reducing costs and saving time from design schedules.
Integrated Design Environment Improves Productivity
The unified analysis environment in the PrimeTime Suite enables designers to perform complete timing, signal integrity, timing constraint, power and variation-aware analysis in a single environment. This improves designer productivity, reduces setup steps, as well as minimizes the number of interface files created and used. It also leads to faster time-to-results because identical operations, such as timing and slew calculations, are not repeated. Costs are minimized by eliminating the need for multiple point tools with associated support costs.
Fast Turn-around Time
PrimeTime offers a range of solutions to reduce time required for analysis and signoff. Highly scalable multicore support reduces the time required for static timing and signal integrity analysis by taking advantage of the runtime benefits of threaded parallel processing. Distributed Multi-Scenario Analysis (DMSA) allows multiple scenarios to be run concurrently, which reduces wall clock time and produces a single comprehensive timing report.
PrimeTime’s performance and capacity is improved release over release to take full advantage of the latest multicore compute hardware available in design farms. PrimeTime uses disk-caching for scalable multi-threading, delivering fast performance in a low memory footprint.
Comprehensive timing and design rule checking, extensive design constraint annotation and delay reporting allow ASIC and COT designers to signoff with confidence knowing that all aspects of their designs have been analyzed.
Advanced node support
PrimeTime supports the latest process node requirements at 20-nm and below. New features include support for multi-valued SPEF parasitics extracted from designs created with Double-Patterning Technology (DPT) and ultra-low voltage FinFET technology support.
The PrimeTime static timing analysis solution is the most trusted and advanced timing signoff solution for gate-level designs. It is the standard for gate-level static timing analysis with the capacity and performance for 500+ million instance chips being designed at 28- nm and below. PrimeTime static timing analysis and StarRC™ parasitic extraction are key components of the Galaxy™ Implementation Platform.
The solution provides designers with extensive timing analysis checks, on-chip variation analysis techniques, golden delay calculation, advanced modeling, unmatched productivity and ease-of-use, a graphical user interface, and industry-wide ASIC vendor signoff and foundry support.
PrimeTime provides the foundation and environment for a suite of extensions in signoff analysis. In addition to timing analysis, PrimeTime SI, PrimeTime ADV, PrimeTime PX and PrimeTime GCA deliver extensions for signal integrity analysis, advanced ECO guidance and variation-aware analysis, leakage and dynamic power analysis and timing constraint analysis.
Golden Delay Calculator
PrimeTime’s built-in RC delay calculator uses parasitic information and Composite Current Source (CCS) libraries to calculate cell and interconnect delays with SPICE-like accuracy. The delay calculation and parasitic annotation reporting capabilities enable designers to debug and pinpoint timing problems. The PrimeTime delay calculator supports voltage and temperature scaling between libraries. This enables multi-voltage analysis without the need to maintain a large collection of libraries for each unique process-voltage-temperature (PVT) point.
Advanced On-Chip Variation (AOCV) Analysis
At 65-nm and above, the traditional approach of using a global derate margin to account for on-chip variations (OCV) can provide margin control to account for process variation. At process nodes below 65-nm PrimeTime’s advanced on-chip variation (Advanced OCV) modeling capability extends OCV analysis to deliver an improved method of adding margin in a design. Advanced OCV uses context-specific derate factors that consider location and logic depth of each path being analyzed providing a more accurate method of assigning on-chip variation margin.
Distributed Multi-Scenario Analysis (DMSA)
Signoff verification requires analysis of many individual scenarios that represent different operational modes and voltage, and temperature and process corners. Analyzing and managing the analysis of these scenarios is simplified with PrimeTime’s Distributed Multi-Scenario Analysis (DMSA) capability. DMSA allows designers to run distributed timing analysis, and ECO guidance simultaneously across multiple scenarios, thereby reducing overall turnaround time. Accompanying visualization capabilities accelerate the debug of multi-scenario analysis results.
Additional Features in PrimeTime
- Advanced modeling capabilities with Interface Logic Models (ILM) and Extracted Timing Models (ETM)
- UPF (Unified Power Format) support
- Graphical User Interface (GUI) enabling timing analysis and design visualization using schematics, histograms, tables, and tree graphs
- Session save and restore
- ASIC vendor signoff and foundry support
- Extensive support for industry-standard input and output file formats
With shrinking process geometries and rising clock frequencies for nanometer designs, signal integrity (SI) effects such as crosstalk delay and noise (or glitch) propagation can cause functional failures or failed timing.
The PrimeTime SI solution extends the PrimeTime static timing analysis and signoff environment by adding accurate crosstalk delay, noise (glitch), and voltage (IR) drop delay analysis to address signal integrity effects at 90-nm and below.
Easy Deployment and Use
PrimeTime SI is easy to use and adopt. It utilizes the familiar PrimeTime flow and environment, with common commands, user interface, reports, and attributes. (See figure 2)
Figure 2: PrimeTime SI flow – Easy to use and adopt
Comprehensive SI Analysis
The unified approach of signal integrity and timing analysis delivers a comprehensive and time-efficient method to analyze noise and crosstalk delay effects on timing. Analysis in a single tool enables faster results while improving designer productivity.
Accurate Crosstalk Delay, Noise (glitch) and IR Drop Analysis
Signal integrity effects are interdependent and need to be analyzed in the context of timing. PrimeTime SI uses an integrated delay calculation engine with the PrimeTime static timing analysis engine to accurately model and compute timing deviations due to crosstalk and IR drop. (See figure 3). PrimeTime SI has the capacity and performance to perform accurate noise calculation, detection, and propagation on the largest of today’s designs.
Multi-Scenario ECO Guidance
PrimeTime’s signoff-accurate ECO guidance enables a fast ECO closure flow. Optimum fixes for both timing and DRC violations are identified using the composite view available in the PrimeTime multi-scenario timing environment, avoiding iterative bottleneck analysis associated with multi-scenario ECOs. PrimeTime’s integrated ECO solution offers timing-aware DRC fixing for maximum capacitance, transition and fanout, and timing fixes that honor DRC.
Figure 3: Crosstalk delay analysis pinpoints crosstalk timing failures.
ECO guidance is resource efficient, working either on a single box or a distributed compute farm. In the event that limited hardware resources are available, ECO can be completed where the number of scenarios is less than the number of available hosts.
Simultaneous Multi-voltage Aware Analysis
Multi-voltage designs require exhaustive analysis of cross voltage domain paths to ensure all worst case paths are identified under all voltage combinations. Simultaneous multi-voltage aware analysis (SMVA) completes analysis of all crossdomain paths under all voltage scenarios in a single run, without the need for margining that can add pessimism.
Additional Features in PrimeTime SI
- Reduces false violations by considering slew propagation, timing windows, and logical correlation of signals
- Advanced waveform propagation accounts for waveform distortions at 20-nm and below that can impact timing
- Multi-voltage support
- SPICE deck output
- Includes HyperScale next generation Hierarchical Timing Analysis technology
- Hierarchical SI analysis capabilities using ILMs with crosstalk
PrimeTime ADV offers advanced technology to extend the scope of signoff-driven ECO closure, and provide a next-generation on-chip variation solution.
Physically-aware Multi-Scenario ECO Guidance
Physically-aware ECO Guidance works closely with IC Compiler’s Minimum Physical Impact (MPI) technology, allowing routing and placement-aware timing and DRC violation fixes that maximize fix rates by minimizing disruption to an existing layout; something that’s especially important for congested designs.
ECO Leakage Recovery
PrimeTime ECO Guidance can take advantage of positive timing slack to identify leakage power reduction changes to the netlist without creating new timing violations.
Figure 4: PrimeTime ECO Leakage Recovery Flow
Multi-scenario signoff driven analysis ensures leakage recovery with no disruption to timing or DRC.
ECO Sequential cell sizing
PrimeTime ECO offers the option to further improve ECO setup and hold fix rates by sizing sequential cells. To ensure best results, either driver or receiver sequential cells can be resized as necessary. Sizing is footprint-compatible to ensure best convergence with implementation.
Parametric On-Chip Variation (POCV)
POCV is the next generation of variation analysis targeted at 14/16nm and below processes. It provides a lightweight statistical margining approach to variation margining. It offers Graph-based Analysis (GBA) pessimism reduction, improved PrimeTime ECO turnaround time, and simpler library characterization than the Advanced OCV approach.
Advanced Latch Analysis
PrimeTime ADV provides analysis of the latch-based designs used in powersensitive applications. Both PrimeTime timing analysis and ECO guidance take the timing characteristics of latches into account. Support for advanced latch analysis allows ECO fixes to be appropriately distributed up- and downstream from latches.
PrimeTime GCA improves designer productivity through look-ahead timing constraint analysis and debug technology tuned for the Synopsys Galaxy Implementation Platform. Early feedback on constraint quality leads to more efficient runtimes and better quality of results in synthesis and physical implementation and static timing analysis tools.
It provides an intuitive interactive environment for designers to assess the correctness and consistency of timing constraints. This helps to eliminate trialand- error iterations during implementation and results in more predictable schedules.
PrimeTime GCA can be run pre- or post-layout to improve constraint quality input to the implementation and signoff process.
Look-ahead Constraint Analysis Technology
With increased design size and expanded use of IP design blocks, there has been a major increase in the size and complexity of timing constraint specification files. Incomplete, inconsistent or conflicting constraints can cause optimization and implementation tools to run ineffectively or to never converge. PrimeTime GCA provides a comprehensive set of rule checks designed to maximize the efficiency of Design Compiler synthesis, IC Compiler physical implementation, and PrimeTime timing signoff.
PrimeTime GCA uses its timing engine to ensure correct interpretation and propagation of constraints. It runs constraint analysis on multi-million gate designs in minutes. In combination with interactive analysis and debug capabilities, the tool identifies and proposes fixes for constraint issues. PrimeTime GCA can check consistency between block and chip level constraints, or between different versions of constraints for the same design.
PrimeTime GCA includes comprehensive timing rule checks which cover pre- and post-layout timing conditions. Users have the ability to create rule classes which allow them to customize the rulesets for a given phase in the design process or to create custom rules specific to their design style or design guidelines.
Easy to deploy
PrimeTime GCA shares a common core user interface with the Galaxy Implementation Platform tool suite. Scripts from Design Compiler, IC Compiler and PrimeTime can be run without modifications.
PrimeTime GCA constraint checks can be run standalone or directly from PrimeTime.
Figure 5: PrimeTime GCA Debug Environment
Additional Features in PrimeTime GCAMode Merging
Extensive debug solution
PrimeTime GCA has extensive support for debug of constraint violations. The tool allows users to debug reported violations in real time using the interactive graphical user interface.
With increased design complexity available at smaller process nodes comes the need for additional operating and test modes. This can increase the number of scenarios required for timing closure and signoff. PrimeTime mode merging technology identifies superset modes (M1, M2 and M3 in Figure 6) that together replicate how a given design is constrained by the original individual mode constraints.
Mode merging uses the PrimeTime distributed multi-scenario analysis (DMSA) infrastructure, and can be added to an existing PrimeTime setup for a multi-scenario design.
PrimeTime mode merging technology offers an up-front assessment of how well a given set of modes can be merged; highlighting constraint conflicts that prevent merging and avoiding timing discrepancies between merged and unmerged constraints.
Figure 6: Mode Merging – Compatibility Graph
The PrimeTime PX solution expands the PrimeTime timing and signal integrity environment to deliver dynamic and leakage power analysis. Designers have a single, unified analysis environment for timing, signal integrity and power analysis that is anchored by the PrimeTime static timing solution.
By combining timing, signal integrity and power analysis into a single tool environment, common operations (e.g. netlist and parasitic reading) are not repeated. The PrimeTime PX solution delivers up to two times (2x) faster time-to-results (TTR) over separate, standalone solutions. As an integral part of the PrimeTime environment, power analysis can be performed using PrimeTime commands, reports, attributes and debugging features. (See figure 7)
Figure 7: PrimeTime PX flow
Full-Chip Timing, SI and Power Analysis
The unified analysis environment allows designers to perform leakage and dynamic power analysis along with timing and SI analysis.
Designers can understand the tradeoffs and effects of leakage and dynamic power in the context of complete timing, signal integrity and power analysis by adopting the easy-to-use PrimeTime PX methodology.
Vector-Free Dynamic Power Analysis
Vector-free dynamic power analysis allows power analysis to be performed without waiting for switching data from simulation. By using the PrimeTime tool’s accurate timing windows, vector-free analysis enables power analysis early in the design flow to identify blocks with the highest power consumption sooner.
Statistical Leakage Power Analysis
Statistical leakage power analysis in PrimeTime PX extends PrimeTime suite’s statistical technology to leakage variation analysis for advanced designs at 65-nm and below. Variation-aware leakage power analysis in PrimeTime PX reduces the leakage signoff pessimism associated with using multiple process corner libraries. An intuitive, easy-to-use graphical user interface enables designers to make efficient yield versus leakage tradeoff decisions for their most complex power-sensitive designs.
Additional Features in PrimeTime PX
- Event-based dynamic power analysis using VCD or SAIF
- RTL and gate-level VCD and SAIF support
- Instantaneous and cycle-accurate peak power analysis
- Average power analysis
- State-dependent leakage power analysis
- Analysis of advanced low power design techniques: multi-voltage, coarse-grain MTCMOS
- Clock tree power estimation
- Power analysis driver GUI window
- Distributed Peak Power Analysis
- UPF support
- Supports industry-standard NLDM and CCS Power libraries
Signoff Modeling and Platform Support
The PrimeTime Suite provides a wide range of advanced modeling support. Interface Logic Models (ILM) are provided for hierarchical static timing analysis. Extracted Timing Models (ETM) are provided, in .lib format, for cell-based reusable IP and physical design flows. A complete set of validation, debugging and model merging features are also provided. HyperScale hierarchical analysis technology offers hierarchical analysis and signoff, with the information captured in saved sessions acting as block models.
The following platforms are supported: AMD64, Sparc64, Linux32 4.0, SUSE 32 and SUSE 64
About Galaxy Implementation Platform
The Galaxy Implementation Platform is a comprehensive solution for cell-based and custom IC implementation. Galaxy accepts design intent in industry standard formats and generates a production ready IC design in GDSII format. Galaxy RTL and Physical implementation products concurrently balance design constraints by performing intelligent tradeoffs between speed, area, power, test and yield. Galaxy Signoff engines accurately model complex physical interactions to ensure signal and power integrity. Coherent algorithms for parasitic extraction and timing produce correlated results.
The Galaxy Implementation Platform provides a comprehensive suite of tools that are being deployed worldwide targeting established process node designs as well as emerging process node FinFET designs at 20nm and below.