Bridging Digital and Custom Domains
Digital and custom (mostly meaning analog) design domains have remained stubbornly separate for a long time...But chips aren’t so neatly segregated now [and] the two flows don’t really work together well. Synopsys recently announced an improvement to this process that provides for a seamless, lossless transfer of information back and forth between domains.
Oct 17, 2011

Using compression to meet pin-limited test requirements
This article looks at the industry’s growing need to maintain high scan compression with fewer test pins, and how Wolfson Microelectronics used DFTMAX compression to meet its pin-limited test requirements.
Jan 21, 2010

Small Delay Defect Testing
Advances in Synopsys’ TetraMAX ATPG technology have made it possible for semiconductor companies to efficiently target extremely subtle nanometer defects during manufacturing test. This article describes the basic principles behind small delay defect (SDD) ATPG and presents failure statistics on hundreds of thousands of ICs manufactured at STMicroelectronics showing that TetraMAX’s SDD patterns achieve higher defect coverage than standard transition delay patterns.
Jun 01, 2009

Flexible Analysis is Key to Power Integrity
Find out why millions of business professionals turn to LexisNexis® to gain unique insights and make informed decisions.
Oct 17, 2008

Accellera Rolls Power Plan
Welcome to EETimes, where engineers make their own connections. Meet your peers, discuss your work, find a mentor, talk tech, get advice, sound off, make some "inside" contacts, expand your career.
Oct 17, 2008

Synopsys revamps IC Complier with multi-threaded routing technology
Developed from scratch by a team assembled specifically for their routing design experience, Mountain View, Calif.-based semiconductor design and manufacturing software supplier Synopsys Inc today rolled out Zroute, a new multi-threaded router that is completed integrated into the company’s IC Compiler physical design software.
May 27, 2008

Design Challenges Drive Need for New Routing Architecture
Timing, area, power, and signal integrity have traditionally been the primary objectives of design technology. Increasingly manufacturability and yield have also become critical design objectives, especially for technology nodes at 90 nanometers (nm) and below.
May 27, 2008

Early relief for 45-nm routing congestion
Moore's Law is both a blessing and a curse. Each new manufacturing process generation provides designers an opportunity to squeeze roughly twice the circuit functionality into an unchanged die area, significantly lowering fabrication costs for systems-on-chip (SoCs).
Apr 07, 2008

Synopsys tries to organize its efforts in EDA multiprocessing
It’s hard to imagine a set of applications that need computing resources more than the chain of EDA tools for a 65 nm chip design. (OK, searching for extraterrestrials, maybe, but the economics are a bit different there.)
Mar 10, 2008

Complex SoC Testing with a Core-Based DFT Strategy
With scaling technology and increasing design sizes, power consumption during test and test data volume have grown dramatically — making it almost impossible to test an entire design once it reaches manufacturing.
Feb 26, 2008

Optimizing Compression in Scan-based ATPG DFT Implementations
Implementing scan compression on-chip provides significant test cost savings, but how much compression is enough? This article introduces a comprehensive economic model unifying test data reduction and test time reduction principles that describes how to determine the optimal compression level for your designs.
Mar 01, 2007

Test Methods Identify Small Delay Defects
Today's systematic and more subtle random defects are not only decreasing yields, but are also increasing the number of test escapes, or defective parts per million (DPPM) shipped out.
Oct 30, 2006

Synopsys donates technology to Accellera low power effort
SAN FRANCISCO — Top-tier EDA vendor Synopsys Inc. said Tuesday (Sept. 19) it has donated power management technology to the Unified Power Format (UPF) standardization effort of EDA standards organization Accellera.
Sep 19, 2006

Power integrity analysis for billion-transistor full-custom designs
While the move to advanced process technologies has enabled levels of integration to reach new heights, engineers must now work harder than ever to realize those benefits.
Sep 17, 2006

Critical area optimizations improve IC yields
The move to advanced nanometer nodes and new process materials is diminishing semiconductor designers’ ability to estimate and realize device yields.
Jan 09, 2006

NewsArticlesBlogsSuccess StoriesWhite PapersWebinarsVideos