The Laker Blitz is a chip-level layout editor for chip finishing operations that accelerates the handoff of large, high-density designs to manufacturing. Laker Blitz allows users to:
- Reduce final tapeout-tomanufacturing cycles
- Ensure high-quality designs with fast full-chip debug
- Diminish the cost of IP merging
Lightning-fast Chip Finishing
Laker Blitz is optimized for speed and productivity during the final steps of the physical design process. It uses innovative database technologies to dramatically speed the import, editing and export of the massive GDSII data files associated with today’s advanced-node SoCs and large chip implementations. The Blitz technology enables high-speed access to chip-level layout data with the complete physical design hierarchy, enabling users to:
- Load and view huge GDSII files 5−20X faster than conventional layout editors
- Manipulate layout data for IP merging and SoC assembly applications
- Run cell, window or full-chip DRC reviews and make layout corrections in single environment
Figure 1: The Laker Blitz layout editor
More than a Viewer
Laker Blitz is built on the same production-proven infrastructure used by the Laker Custom Layout System, upon which hundreds of companies have deployed design flows to produce high-quality chip layouts. It leverages the core suite of Laker layout editing commands and its unmatched tool interoperability to help designers reduce the time and effort required to achieve final tapeout.
- Built-in net highlighting capabilities to rapidly trace critical nets for full-chip debug
- Automated data manipulation with extensive library of Laker Tcl extensions
- Integrated DRC with all top-tier signoff tools, including IC Validator and Calibre
- Laker APIs for internal chip finishing and third-party tool integration
Superior Results with Less Effort
As with all software offerings in the Laker custom IC design and layout automation solutions, Laker Blitz enables users to achieve superior results with less effort. It brings together a high-speed, high-capacity database and proven layout technologies that are ideally suited to the chip finishing requirements of semiconductor manufacturers, foundries and fabless design companies.
Laker layout users appreciate the familiar, easy-to-use graphical interface of the Laker Blitz environment and its compatibility with existing Laker data manipulation and DRC capabilities. New Laker users realize measurable improvements in productivity with more robust chip-level editing features compared to the limited scope of current generation ‘flat’ layout viewers. At the same time, all Laker Blitz users benefit from the dramatic performance boost optimized for critical chip finishing tasks that are otherwise painfully slow with conventional layout editors.