Synopsys’ FPGA design solution is a comprehensive suite of tools that deliver the industry’s best results for both timing performance and area optimization. This suite is comprised of Synplify® synthesis, Synphony Model Compiler for DSP design, Certify® enabling multi-FPGA partitioning, and Identify® RTL Debugger. The combination of these solutions provides designers with the necessary tools to delivery any FPGA based design to market faster and with the best quality of results required for today’s complex FPGA designs.
Synplify® synthesis delivers world class technology for fast synthesis algorithms, along with multi-processing, hierarchical and incremental design technologies that enable designers to achieve timing closure with the highest productivity rate. Synplify® synthesis coupled with Identify® RTL Debugger provides developers with a powerful methodology to instrument and debug their RTL to deliver differentiated product to market faster.
Synphony Model Compiler (SMC) provides a comprehensive, high-level model library for creating math, signal processing, and communications designs in the Simulink® environment. This enables designers save months in design and verification of signal processing hardware and systems with signal processing IP, best QoR across any technology and high-performance verification.
To learn more about Synopsys' FPGA design tools, read the whitepapers or download a FREE product evaluation of Synplify.