FPGA Design 

Better Results Accelerate Innovation 

Synopsys’ FPGA design solution is a comprehensive suite of FPGA implementation and debug tools that deliver the industry’s best quality of results for both timing performance and area optimization. Fast synthesis algorithms, along with multi-processing, hierarchical and incremental design technologies, deliver the accelerated timing closure and time-to-market that is required for today’s complex FPGA designs.  Integrated debug technology allows designers to work directly in their RTL code making it much more productive and intuitive than the typical method of debugging synthesized gates.  As soft errors such as Single Event Upsets (SEUs) resulting from atmospheric radiation have become more common at ground level, applications involving human safety increasingly require SEU mitigation techniques. Synopsys has automated technologies to both detect and correct such soft errors in FPGAs. Synopsys FPGA solution is technology and vendor independent, allowing designers to quickly retarget from one FPGA vendor device to another from a common, easy to use, environment.

To learn more about Synopsys’ FPGA design tools, read the whitepapers or download a FREE evaluation of Synplify.

Compare Synthesis Product Features

PDFSynplify Premier Product Brochure

PDFHigh-Reliability Brochure

  • Design Tools
 

Synplify Pro
Logic Synthesis for FPGA Implementation


Synplify Premier
Fast implementation of advanced FPGAs and FPGA-based prototyping

  • DSP Design
  • High-level synthesis and accelerated verification for signal processing  

Synphony Model Compiler
Faster, More Efficient ASIC & FPGA HW Development for DSP Algorithms

  • FPGA Debug Tools
  • Integrated RTL debug and visibility enhancement 

Identify RTL Debugger
Simulator-like visibility into FPGA hardware operation


HAPS
High-performance ASIC Prototyping System™


ProtoCompiler
Design automation and debug for the HAPS Series


Certify
Multi-FPGA implementation and partitioning


Synplify Premier
FPGA synthesis for ASIC prototyping

  • High-Level Synthesis
  • High-level synthesis from language and model-based designs 

Synphony C Compiler
High-level synthesis to accelerate design of image processing IP

  • Simulation
  • High-performance functional verification 

VCS
High-performance simulation


Leda
Static design and coding guideline checker


VCS Verification Library
The broadest verification IP (VIP) library in the industry

  • DesignWare IP
  • The industry's most widely used, silicon-proven IP  

DesignWare IP
The industry's most widely used, silicon-proven IP

  • Mil/Aero Solutions
  • High-reliability FPGA solutions including DO-254 support 

Synplify Premier
Design automation for SEU mitigation in FPGAs


DO-254 Compliance
DO-254 Solution for airborne electronics
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