IC Compiler White Papers 

 

Overview
IC Compiler is a single, convergent, chip-level physical implementation tool that includes flat and hierarchical design planning, placement and optimization, clock tree synthesis, routing, DFM, and low-power capabilities. The IC Compiler white paper series addresses key concerns that you are facing today such as low power, 45nm DFM routing, and large hierarchical designs. Also included are topics on In-Design physical verification with IC Validator, which enables you to run DRC and practical DFM steps alongside place and route within the familiar IC Compiler physical design environment. Check back often as additional white papers will be added throughout the year.

Multi-Source CTS Delivers Flexible High Performance and Variation Tolerance
Multi-source clock tree is a hybrid containing the best aspects of a conventional clock tree and a pure clock mesh. This paper illustrates the benefits such as lower skew and better on-chip-variation (OCV) performance compared to a conventional clock tree.

IC Validator: Automatic DRC Repair
This paper presents how in-design physical verification with IC Validator enables Automatic DRC Repair (ADR), a novel capability that makes it possible for designers to automatically detect, repair and revalidate signoff DRC violations with negligible physical or timing impact, all within IC Compiler.

Minimizing Time to Complete a Hierarchical Design
This paper addresses design exploration and planning in a hierarchical flow for larger SoCs and discusses techniques for achieving predictable design convergence without surprises.

IC Validator: GDS Merge
This paper presents an optimal approach to creating a working snapshot of a design’s complete mask data set for the purposes of in-design physical verification with IC Validator, Synopsys’ award-winning physical verification platform for advanced nodes.

IC Validator: Physical Verification for Analog Designs
Physical verification challenges of analog designs are different than the challenges of large digital designs. IC Validator, the latest generation physical verification tool, can be used to address these challenges. This paper addresses many of the physical verification requirements of analog designers and how they are met with IC Validator.

Multicorner-Multimode – A Necessary and Manageable Reality of Design
This paper addresses the increasing design complexity and process variability present at 65nm and amplified at 45nm and below, and the pressing need for a concurrent, convergent, correlated, multi-corner multi-mode implementation solution. Complexity and variability are the drivers for an increasing number of design modes and process corners.

Physical Datapath – Improved Productivity for All Designs
An ideal physical datapath solution for custom and ASIC designs should have an automated flow to deliver performance power area (PPA) objectives with predictable time-to-results (TTR). Currently, most EDA tools do not provide a solution that addresses the limitations of a custom datapath flow. This paper discusses datapath designs, benefits, limitations, and the use of an automated datapath design capability that allows both custom and ASIC designers to meet aggressive design objectives with ever-tighter project deadlines.

Achieving Faster Time-to-Tapeout with In-Design Sign-Off Metal Fill
By providing foundry signoff metal fill generation in an interface that is familiar to the place and route engineer, a cumbersome collection of design tasks is turned into a pushbutton flow. Additionally, control over insertion and deletion of fill layers provides added benefit for engineering change orders (ECOs) when minimal schedule delay is imperative. Timing impact is considered as the fill is generated during the implementation stage so that both DRC’s and timing are taken into account simultaneously. Achieving correct-by-construction results during implementation significantly reduces time to tapeout and avoids schedule delays. This paper presents a pushbutton flow to generate timing-aware, signoff quality metal fill during place and route.

Accelerating Physical Verification With an In-Design Flow
Physical designers are responsible for verifying and ensuring that their designs are clean of Design Rule Check (DRC) violations before delivering the design to the foundry. Since semiconductor foundries use sign-off DRC rules to validate the manufacturability of a design, physical designers must use the same sign-off DRC rules to avoid any missing checks. This paper discusses the need for a concurrent physical design and physical verification flow, also known as an in-design physical verification flow. This flow improves the overall turnaround time and ease of use of the physical verification process. This paper also provides a production-proven example of this flow.

Realizing Low Power IC Design: It Starts with the Clock Tree
There are numerous techniques to achieve a low-power design and several approaches to structuring the flow. As a starting point, high performance designs require a benchmark proven low-skew, low-insertion delay CTS solution. Correlation to industry standard sign-off engines for accuracy and minimum data format translations are required to achieve fast design closure. The optimal solution includes complete low power capability throughout the design flow. This paper addresses low power design issues and includes technologies and techniques to achieve high performance, low power design goals.

Advanced Design Challenges Make DFM-Friendly Routing A Must-Have
Timing, area, power, and signal integrity have traditionally been the primary objectives of design technology, and the primary care-abouts for designers and CAD engineers. Increasingly manufacturability and yield have also become critical design objectives, and multiple design-for-manufacturability (DFM) optimization techniques have been added to the design flows. As manufacturability has been a secondary goal, conventional routers have been optimizing for it after timing optimization – the point at which all of the primary design goals have already been met. While this methodology has worked well up to the 65nm technology node, it starts to break down at 45nm and below. This paper talks about the routing challenges at 45nm and below and the need for modern DFM-friendly routing technologies for achieving better manufacturability and higher yield without sacrificing performance.

Clock Mesh for Mainstream Designs: Designing High Performance Variation Tolerant Circuits
By its very nature, even the best conventional clock tree synthesis leaves both performance and variation tolerance potential on the table. Clock mesh offers the designer a means of achieving extreme high performance along with the avoidance of process variation effects. Long known as the clock distribution method for high-end microprocessors, clock mesh also offers significant variation tolerance. Clock mesh use to be an entirely manual, difficult to analyze technology, but new advances in clock mesh automation and analysis now enable it to be considered as a mainstream clock distribution solution.



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