Introducing IC Compiler II 

Hear what Designers are saying about IC Compiler II

 

Antun Domic Introduces IC Compiler II

IC Compiler II is a complete place and route system that enables 10X faster throughput for designs across all process nodes. Hear what Antun Domic, executive vice president and general manager of Synopsys' Design Group, has to say about this new physical implementation solution.

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IC Compiler II
IC Compiler II is a complete netlist to GDSII place-and-route system that enables 10X faster throughput for designs across all process nodes, while improving final quality of results (QoR). IC Compiler II is specifically designed to address today's hypersensitive time-to-market pressures while delivering best-in-class solutions for flat and hierarchical design planning, early design exploration and prototyping, placement and optimization, clock tree synthesis, routing, manufacturing compliance, and low-power challenges.



IC Compiler at DAC 2014

IC Compiler II is a complete netlist to GDSII place-and-route system that enables 10X faster throughput for designs across all process nodes, while improving final quality of results (QoR). IC Compiler II is specifically designed to address today's hypersensitive time-to-market pressures while delivering best-in-class solutions for flat and hierarchical design planning, early design exploration and prototyping, placement and optimization, clock tree synthesis, routing, manufacturing compliance, and low-power challenges.



IC Compiler II Launch at SNUG-SV

The IC Compiler II launch at SV SNUG was well received by large in-person audiences. This video captures the keynote address, the luncheon event where key customers shared their experiences using IC Compiler II, and the R&D panel where the Synopsys technologists shared deep insights into the inner workings of the new architecture and algorithms. Share the launch experience through this short video.



R&D Insights

IC Compiler II Core Infrastructure
Mark Bales, Synopsys Scientist, explains the new IC Compiler II infrastructure and how it enables 10X faster throughput.

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IC Compiler II Optimization
Thomas Andersen, Group Director R&D, provides an overview of physical optimization in IC Compiler II and how the new global-analytics- based framework enables high QoR along with fast, hierarchical full chip closure.

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IC Compiler II Clock Synthesis
Aiqun Cao, Principal Engineer, discusses how IC Compiler II’s new clock synthesis delivers faster design convergence with automated variation-tolerance.

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IC Compiler II Design Planning
Neeraj Kaul, Group Director R&D, discusses hierarchical design planning in IC Compiler II and how the new data and tool architectures enable unprecedented design capacity and throughput.

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