Physical Implementation 

Comprehensive Place and Route  

Physical implementation in the Galaxy™ Design Platform provides an industry-leading, production-proven solution with
IC Compiler and IC Compiler II. IC Compiler II is a complete netlist to GDSII place and route system that enables 10X faster throughput for designs across all process nodes. Re-architected from the ground up to deliver unsurpassed scalability, IC Compiler II introduces a new design infrastructure complete with a compact data model and a single timer engine. Both flat and hierarchical designs of all sizes benefit from the new technological advances in IC Compiler II including native multi-core, native multi-voltage, and native multi-hierarchy support.


A complete place and route system that enables 10X faster throughput for designs across all process nodes

As an integral part of Synopsys’ Galaxy Design Platform, IC Compiler delivers place and route for established and emerging process nodes

  • Talus
  • Netlist-to-GDSII implementation for designs at or above 28nmmore

Netlist-to-GDSII implementation for designs at or above 28nm

Provides early estimates of area, timing and routability

Key Benefits
  • Complete netlist-to-GDSII solution for best Quality-of-Results and Time-To-Results
  • High throughput for designs in mainstream technologies
  • High performance for advance silicon technologies
  • Comprehensive optimization capabilities meet timing, area, power, signal integrity, routability and yield objectives
  • Provide predictability during the implementation process
  • Tightly correlated with golden sign-off solutions: PrimeTime SI and Star-RCXT
  • Comprehensive low power including support for multi-voltage designs, MTCMOS, leakage, dynamic optimization and low power CTS
  • Production proven at 45nm and below
  • Concurrent design planning solution for hierarchical and flat designs
  • Zroute multi-threaded technology is 10X faster, enables concurrent DFM optimizations and supports advanced routing rules
  • MinChip automated technology enables smallest routable die size
  • Supports physical test-optimized flow with DFT Compiler and DFT MAX features
  • Easy to Use with powerful GUI and Tcl support throughout
  • Supports industry standard input/output Interfaces

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