IC Validator is a complete physical verification tool, performing the increasingly complex DRC and LVS sign-off checks. In addition, it has been specifically architected for In-Design physical verification. In-Design physical verification means that the Place and Route engineers can run DRC and practical DFM steps alongside place and route within the familiar IC Compiler physical design environment.
In this video, Synopsys Chairman and CEO, Dr. Aart de Geus shares his view on the broad and rapid adoption of this new technology and how it could change physical verification going forward.
IC Validator is a full, sign-off quality verification tool that delivers the highest performance to enable significantly improved time-to-tapeout with better DFM closure. Hear what Antun Domic, senior vice president and general manager of Synopsys' Implementation Group, has to say about this new physical verification solution.