PrimeYield FAQs 


General Questions

What is being announced?
Synopsys has announced PrimeYield, a comprehensive tool suite for design-yield analysis. PrimeYield accurately predicts design-induced mechanisms that threaten yield in highly sensitive process areas and provides automated correction guidance to upstream design implementation tools. The primary value for the designer is the creation of more robust designs by decreasing sensitivity to process variations.

Why is Synopsys offering this tool?
In the past, the manufacturing side has borne the brunt of the responsibility for ramping and maintaining high production yield. The game has changed, and at 65nm and below, it is no longer possible for designers to create a high-yielding device simply by following the design rules. As a result, designers are demanding solutions that provide insight into key yield-limiting issues, with the goal of understanding potential yield problems before committing to tapeout. Synopsys PrimeYield answers the designer’s call by providing critical analysis capabilities.

Can you tell me more about PrimeYield? What does PrimeYield contain?
To address critical yield issues, the PrimeYield tool suite comprises the following modules:

PrimeYield LCC - Lithography Compliance Checking (LCC), which flags potential lithographical errors and process-variation effects for the designer earlier in the design process

PrimeYield CMP - Model-based Chemical-Mechanical Polishing (CMP), which locates and analyzes uneven metal fill, a major source of systematic failures in advanced chip designs; and

How does PrimeYield LCC work?
PrimeYield LCC simulates the full resolution-enhancement technology (RET) tapeout flow using the same production-baseline technology and manufacturing models used by today’s leading foundries and integrated device manufacturers, and reports lithographic sensitivities in the layout. These problems range from excessive line narrowing and potential line shorting to poor contact and via overlap with metal. PrimeYield LCC ranks these problems by severity and presents them to the designer for review. For customers who own IC Compiler, the problems can be repaired automatically, based on a set of coded correction rules.

Why is PrimeYield LCC necessary? I’m already following my design rules and haven’t seen any yield problems in my 90nm chips.
Foundries understand the process sensitivities inherent in today’s advanced process nodes and offer both “minimum” and “recommended” rules for critical layout geometries. At 65nm, it is very difficult to produce a high-yielding design by following the minimum rules, yet it is overly conservative to use recommended rules throughout the entire design. PrimeYield LCC gives designers insight into their design’s manufacturability and confidence that potential catastrophic failures will be caught.

What problems does PrimeYield CMP address?
At 65nm, the surface planarity of a design metal layer is dependent on two factors: the relative metal density for the layer and the cumulative effect of non-planarity in the lower design layers. This is due to the nature of the copper process and the sensitivity of copper to the CMP step. Historically, the CMP problem has been addressed by adding dummy metal to a layer using a rule-based approach. This technique falls short at 65nm, where a model-based analysis approach is required.

How does PrimeYield CMP work?
PrimeYield-CMP begins by tiling the design, then extracting CMP-related layout parameters for each tile and metal layer from the GDS or Milkyway™ database. These parameters include data on metal density, perimeter and other information. Next, the CMP simulator uses these parameters to create a density and thickness profile for each metal layer. A “heat map” is constructed from these profiles, showing a color-coded grid indicating the relative density or thickness for each tile in the design. The designer uses this heat map to identify design areas that are non-planar and may cause design problems. This same data is also available in a report.

If I already have a dummy fill methodology with Hercules™, why do I need PrimeYield CMP?
While the rule-based approach to dummy fill has been effective for earlier technology nodes, it is no longer viable at 65nm. In those older approaches, metal density is normalized by adding additional metal in the empty space, and by slotting the wide metal channels. These approaches did not consider the cumulative effect of metal fill on subsequent layers. PrimeYield CMP considers the density and thickness of each layer when computing the planarity of a given design layer.


What differentiates PrimeYield from the competition?
Here are the key differentiators (three Cs) for PrimeYield:
  • Correct - PrimeYield is built upon production-baseline technology and manufacturing models used by the leading foundries and integrated device manufacturers (IDMs). None of our startup competitors can claim this tight link to manufacturing.
  • Comprehensive - PrimeYield is the only tool in the industry that combines the identification of the three most important aspects of yield loss at 65nm: sensitivity to lithographic effects, design planarity and random particle defects. No other tool suite in the industry can claim to address all of these areas.
  • Correlated - PrimeYield links back tightly to the Synopsys design implementation flow. These links include automatic litho hotspot correction within IC Compiler, and for parasitic extraction on designs with CMP dummy fill using the Star-RCXT tool for accurate modeling of dummy fill capacitance.