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Design Compiler Graphical
Create a Better Starting Point for Faster Physical Implementation
Continuing the trend of delivering innovative synthesis technology, Design Compiler® Graphical delivers superior quality of results and streamlines the flow for a faster, more predictable design implementation. Design Compiler Graphical uses advanced optimizations combined with accurate net delay modeling to achieve 5% faster timing post-placement. It extends DC Ultra™ topographical technology to provide physical guidance to IC Compiler, tightening timing and area correlation between synthesis and placement to 5% while speeding-up IC Compiler placement by 1.5X.
Benefits
- Advanced optimizations deliver 10% faster timing QoR
- Physical guidance to IC Compiler tightens correlation of timing, area and power to within 5% and speeds placement by 1.5X
- Accurate pre- and post-synthesis congestion prediction and congestion-driven optimization eases routing
- Gate-to-gate optimization for smaller area on new or legacy designs while maintaining timing Quality of Results (QoR)
- Cross-probing between RTL, and design views such as schematic, timing reports and physical views for faster debugging
- Early physical visualization and debugging identifies layout issues prior to physical implementation
- Floorplan exploration for faster design convergence to an optimal floorplan
- 2X faster runtime on quad-core compute servers
- Concurrent multi-corner, multi-mode (MCMM) synthesis
Design Compiler NXT
We strongly recommend using Design Compiler NXT since it encapsulates latest RTL synthesis technology advancements and delivers best results for advanced node designs.