This article looks at the industry’s growing need to maintain high scan compression with fewer test pins, and how Wolfson Microelectronics used DFTMAX compression to meet its pin-limited test requirements.
Jan 21, 2010

Graphics chip vendor NVIDIA has licensed Synopsys' Yield Explorer, a yield management tool said to expedite the discovery and mitigation of yield limiters in leading-edge ICs, to reduce time-to-volume. A complement to Synopsys' TetraMAX diagnostics solution, Yield Explorer links all aspects of the design, manufacturing and test flows into a single data-bank and minimizes design re-spin through rapid and comprehensive capture of design-process-test interactions causing low yield.
Oct 28, 2009

Advances in Synopsys’ TetraMAX ATPG technology have made it possible for semiconductor companies to efficiently target extremely subtle nanometer defects during manufacturing test. This article describes the basic principles behind small delay defect (SDD) ATPG and presents failure statistics on hundreds of thousands of ICs manufactured at STMicroelectronics showing that TetraMAX’s SDD patterns achieve higher defect coverage than standard transition delay patterns.
Jun 01, 2009

Find out why millions of business professionals turn to LexisNexis® to gain unique insights and make informed decisions.
Oct 20, 2008

Find out why millions of business professionals turn to LexisNexis® to gain unique insights and make informed decisions.
Oct 20, 2008

Power-aware ATPG technology controls thermal and power-rail-droop problems that can damage devices or lead to false failures during production test.
Oct 01, 2008

Implementing scan compression on-chip provides significant test cost savings, but how much compression is enough? This article introduces a comprehensive economic model unifying test data reduction and test time reduction principles that describes how to determine the optimal compression level for your designs.
Mar 01, 2007