| Using compression to meet pin-limited test requirements |
This article looks at the industry’s growing need to maintain high scan compression with fewer test pins, and how Wolfson Microelectronics used DFTMAX compression to meet its pin-limited test requirements.
Jan 21, 2010 |
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| NVIDIA licenses Synopsys' yield management tool |
Graphics chip vendor NVIDIA has licensed Synopsys' Yield Explorer, a yield management tool said to expedite the discovery and mitigation of yield limiters in leading-edge ICs, to reduce time-to-volume. A complement to Synopsys' TetraMAX diagnostics solution, Yield Explorer links all aspects of the design, manufacturing and test flows into a single data-bank and minimizes design re-spin through rapid and comprehensive capture of design-process-test interactions causing low yield.
Oct 28, 2009 |
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| Small Delay Defect Testing |
Advances in Synopsys’ TetraMAX ATPG technology have made it possible for semiconductor companies to efficiently target extremely subtle nanometer defects during manufacturing test. This article describes the basic principles behind small delay defect (SDD) ATPG and presents failure statistics on hundreds of thousands of ICs manufactured at STMicroelectronics showing that TetraMAX’s SDD patterns achieve higher defect coverage than standard transition delay patterns.
Jun 01, 2009 |
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| Flexible Analysis is Key to Power Integrity |
Find out why millions of business professionals turn to LexisNexis® to gain unique insights and make informed decisions.
Oct 20, 2008 |
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| Accellera Rolls Power Plan |
Find out why millions of business professionals turn to LexisNexis® to gain unique insights and make informed decisions.
Oct 20, 2008 |
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| Playing it cool |
Power-aware ATPG technology controls thermal and power-rail-droop problems that can damage devices or lead to false failures during production test.
Oct 01, 2008 |
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| Optimizing Compression in Scan-based ATPG DFT Implementations |
Implementing scan compression on-chip provides significant test cost savings, but how much compression is enough? This article introduces a comprehensive economic model unifying test data reduction and test time reduction principles that describes how to determine the optimal compression level for your designs.
Mar 01, 2007 |
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| ITC: Synopsys addresses yield, memory test, and small delay defects |
Synopsys announced links between its TetraMAX ATPG tool and Odyssey yield-management system, touted a collaborative effort with Virage Logic, and said it's working with several customers on small-delay-defect test. In addition, Chris Allsup, marketing manager for test automation products, discussed Synopsys ITC demonstrations in an interview with chief editor Rick Nelson.
Oct 27, 2006 |
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| Synopsys donates technology to Accellera low-power effort |
Top-tier EDA vendor Synopsys Inc. said Tuesday (Sept. 19) it has donated power management technology to the Unified Power Format (UPF) standardization effort of EDA standards organization Accellera.
Sep 19, 2006 |
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| Power integrity analysis for billion-transistor full-custom designs |
While the move to advanced process technologies has enabled levels of integration to reach new heights, engineers must now work harder than ever to realize those benefits.
Sep 17, 2006 |
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| Limits of Test Time Reduction |
Nanometer fabrication processes offer higher circuit density and better performance but also present new challenges. Systematic and random defects that were a nuisance above 90 nm are now killer defects.
Jun 01, 2006 |
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| Critical Area Optimizations Improve IC Yields |
The move to advanced nanometer nodes and new process materials is diminishing semiconductor designers’ ability to estimate and realize device yields.
Jan 09, 2006 |
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