Webinars 

STMicroelectronics and Synopsys Present: How iCube Technology in TetraMAX II is Breaking the ATPG Sound Barrier
With TetraMAX II, Synopsys’ next-generation ATPG and diagnostics solution, pattern generation has been re-engineered to deliver unprecedented speed and efficiency. Following a brief introduction of the product, our guest speaker describes STMicroelectronics’ motivation to achieve faster ATPG turnaround time for high defect-coverage manufacturing tests, and shares his evaluation results. Synopsys then shows how breakthrough “iCube” technology in TetraMAX II generates fewer patterns and enables order-of-magnitude faster runtime than existing solutions.
Robert Mattiuzzo, SoC Integration and DFT Methodologies Manager, STMicroelectronics; Wolfgang Meyer, Director R&D, Synopsys, Inc.; Chris Allsup, Senior Staff Technical Marketing Manager, Synopsys, Inc.
Oct 27, 2016
 
ON Semiconductor and Synopsys: ISO 26262 and Automotive DFT Requirements
In this webinar, you will learn about the ISO 26262 functional safety standard and how it is driving DFT requirements today.
Chanthachith Souvanthong, Corporate Functional Safety Manager, ON Semiconductor; Adam Cron, Principle Engineer, Synopsys, Inc.; Steve Smith, Sr. Marketing Director, Synopsys, Inc.
Sep 22, 2016
 
Selecting the Correct Mathematical Format to Achieve Design Precision
Learn about mathematical requirements for your targeted applications as well as new formats for use in hardware mathematics that can help you make clear design trade-offs and achieve design precision.
Kiran Kumar, Corporate Applications Engineer, Synopsys Inc.
Jul 14, 2016
 
Xilinx and Synopsys Present: Meeting Test Goals Faster with SpyGlass DFT ADV
Early detection of testability issues can prevent major bottlenecks downstream and avoid time-consuming design iterations. In this webinar, Synopsys presents new techniques and capabilities available in SpyGlass DFT ADV such as high-impact test points to boost coverage, reduce the number of patterns, and minimize test costs. Our guest speaker from Xilinx discusses test challenges associated with large SoC designs such as the Xilinx Zynq® UltraScale™ chip family, and illustrates how SpyGlass DFT ADV addresses testability issues early in the design flow, saving weeks of complex DFT-related ECOs.
Amit Majumdar, Principal Engineer, Xilinx; Anthony Joseph, Applications Engineer, Synopsys; Dmitry Melnik, Marketing Manager, Synopsys
Apr 28, 2016
 
Test & Repair of SoCs for Functional Safety Applications
Learn about diagnosis, debug and self-test and repair solutions for memories, logic, AMS and interface IP blocks for automotive requirements to satisfy key criteria like low DPPM.
Yervant Zorian, Fellow & Chief Architect, Synopsys; Faisal Goriawalla, Product Marketing Manager, Synopsys
Apr 12, 2016
 
Sunplus Technology Perspective: Achieving Superior Results and Shorter Schedules with Design Compiler (Traditional Chinese)
Maximizing IC performance and reducing area are key for Sunplus to deliver competitive and cost-effective multimedia products to market while meeting aggressive schedules. In this webinar, John Yeh CAD engineer will discuss how Sunplus uses the latest Design Compiler technologies to improve predictability, reduce schedules and achieve superior results. He will show how DC Explorer helps speed up the development of high quality RTL and constraints and allows early physical exploration. He will also discuss how Design Compiler Graphical enables Sunplus to achieve higher performance and tighter correlation to IC Compiler for faster design convergence.
John Yeh, CAD Engineer, Sunplus Technology
Jan 28, 2016
 
Sunplus Technology Perspective: Achieving Superior Results and Shorter Schedules with Design Compiler (Simplified Chinese)
Maximizing IC performance and reducing area are key for Sunplus to deliver competitive and cost-effective multimedia products to market while meeting aggressive schedules. In this webinar, John Yeh CAD engineer will discuss how Sunplus uses the latest Design Compiler technologies to improve predictability, reduce schedules and achieve superior results. He will show how DC Explorer helps speed up the development of high quality RTL and constraints and allows early physical exploration. He will also discuss how Design Compiler Graphical enables Sunplus to achieve higher performance and tighter correlation to IC Compiler for faster design convergence.
John Yeh, CAD engineer, Sunplus Technology
Jan 28, 2016
 
GUC ASIC Methodology: Higher Predictability and Superior Results with Design Compiler Graphical
Achieving higher performance, lower power and smaller die size in an efficient timeframe is key for GUC’s ASIC design services. In this webinar, Kazuyuki Irie, Department manager for GUC Japan discusses the challenges of a traditional ASIC design flow that required timing margin in synthesis for faster design closure; leading to less than optimal area and power results. He will discuss how GUC Japan recognized a Design Compiler Graphical based methodology that improves predictability, reduces schedule and achieves superior results for GUC Japan.
Kazuyuki Irie, Department Manager, GUC Japan
Oct 08, 2015
 
STMicroelectronics’ Experience: Synopsys Logic BIST for Automotive and Safety-Critical Designs
ICs targeted for safety-critical applications must be able to perform in-system self-test in compliance with functional safety standards such as ISO 26262. In this webinar, Synopsys highlights synthesis-based logic BIST that addresses the self-test requirements for safety-critical designs. Our guest speaker from STMicroelectronics presents results and details of Synopsys’ test solution successfully deployed on production designs.
Cinzia Bartolommei, Senior DFT Engineer, STMicroelectronics; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Jul 30, 2015
 
Advantest and Synopsys: Taking Test Cost Reduction to the Next Level
In this webinar, we highlight two methodologies, multisite test and concurrent test, that minimize test application time and maximize throughput.
Dave Armstrong, Director of Business Development, Advantest; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Apr 30, 2015
 
ARM Perspective: Area Reduction on ARM Mali Cost-Efficient GPUs
In this joint webinar, ARM describes methodologies, design choices and results achieved by an area-centric reference implementation of the ARM Mali GPU using Design Compiler Graphical and IC Compiler.
Pierre-Alexandre Bou-Ach, Physical Design Lead, ARM; Priti Vijayvargiya, Director of RTL Synthesis Product Marketing, Synopsys
Apr 23, 2015
 
Accelerate your design closure with DC Ultra
Join this webinar to hear directly from senior product team members on how you can achieve superior results faster utilizing sophisticated optimizations of DC Ultra.
Sandra Ma, Synopsys; Janet Olson, Synopsys
Apr 21, 2009
 


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