SNUG Silicon Valley 2015: Design Compiler Lunch & Learn

Moore's Law continues to advance, providing designers with more available transistors, increased performance and lower power than ever before. In addition, the enhancement of mature semiconductor technologies enables better silicon utilization, performance and power for a broad range of applications, including automotive, wearable technology and healthcare devices. One thing designers using these technologies share is the drive to accelerate innovation – the lifeblood of a modern semiconductor design company. Watch this video and hear how your peers are leveraging the latest Design Compiler technologies to deliver amazing innovations in their IC products.
Eyal Odiz, VP of R&D, Design Group, Synopsys; Purnabha Majumder, Sr. Manager, Hardware Engineering, NVIDIA; Haroon Gauhar, Principal Design Engineer, ARM

Design Compiler Lunch and Learn: Shrinking Design Area and Schedules for Established and Emerging Nodes

View this video of the 2014 Design Compiler Lunch and Learn and hear users discuss their experiences using new Synopsys synthesis technologies to meet the challenges of complex designs at both established and advanced nodes. You will learn how Design Compiler Graphical helps achieve smaller area, reduced congestion and faster convergence. Additionally, find out how the latest capabilities in DC Explorer help accelerate the development of high-quality RTL.
Eyal Odiz, VP of R&D, Design Group, Synopsys; Santi Adamo, Design Manager, STMicroelectronics; Tatsuya Nakae, Director of SoC Design Methodology, Fujitsu Semiconductor; Hatem Yazbek, Technical Director, Broadcom

Fujitsu’s experience with Design Compiler Graphical and DC Explorer for ASIC handoff [Japanese]
Fujitsu's Customized Flow with Design Compiler – 33% Higher Design Density [Japanese]

Atsushi Tsuchiya, Hardware Design Engineer, Fujitsu

NEW! DC Explorer Demo

Floorplan exploration from RTL
Josefina Hobbs, Technical Marketing Manager, Synopsys and Carlos Abraham, Corporate Applications Engineer, Synopsys

DC Explorer Demo
DC Explorer Demo

Early RTL exploration accelerates synthesis and place & route.
Chris Allsup, Technical Marketing Manager, Synopsys

Formality Ultra Demo

This video demonstration shows how to accelerate implementation of a functional ECO with Formality Ultra.
John Lehman, Senior CAE Manager, Synopsys

Intro to Formality Ultra Video

This video introduces Formality Ultra, a new add-on option to Formality, which extends its equivalency checking technology to significantly accelerate the implementation and verification of functional ECOs.
Antun Domic, General Manager, Implementation Group, Synopsys

Design Compiler Customer Videos
Design Compiler Customer Videos

Industry experts from Samsung, Qualcomm, Cisco and Synopsys discuss how they are utilizing DC Explorer and Design Compiler Graphical to tackle the challenges of ever-increasing design complexities amidst shrinking schedules.
Eyal Odiz, VP of Engineering, Synopsys, Cheal Rim, Sr. Engineer, Samsung, Troung Hoang Principal Engineer/Manager, Qualcomm, Venkataraman Srinivasagam,Technical Leader, Cisco

DC Explorer Video

Introducing DC Explorer
Antun Domic, General Manager, Implementation Group, Synopsys, Inc.

Accelerate Product Ramp with TetraMAX ATPG and Yield Explorer

Girish Patankar discusses diagnostics in TetraMAX ATPG, accuracy improvements with physical diagnostics, and how TetraMAX ATPG and Yield Explorer form a complete solution for volume diagnostics.
Girish Patankar, Sr. R&D Manager

Galaxy Test 2010.03 Introduction

Amy Mitby introduces the latest release and highlights four new powerful features
Amy Mitby, Sr. Test Applications Consultant

Small Delay Defects: The Need for Better At-Speed Tests

Manufacturing process variations can introduce small delays that adversely affect critical design paths, leading to circuit failures. Dr. T.W. Williams introduces technology developed at Synopsys to detect defects creating these delays, thereby increasing the test quality.
Tom Williams, Synopsys Fellow

Perspective: Boost your design productivity

Design Compiler Graphical, the newest member of the Design Compiler product family, creates a better starting point for physical implementation and can shave weeks off your design schedule.
Antun Domic, senior vice president and general manager of Synopsys' Implementation Group

Pin-Limited Test

Current trends are accelerating the need for pin-limited test. Amy Mitby introduces capabilities in DFTMAX compression that allows designers to achieve predictable compression of up to 100X or more with only one pair of test data pins.
Amy Mitby, Sr. Test Applications Consultant

Power-Aware Test

Conventional compression tools create patterns that force the device under test to consume up to ten times more power compared to normal operation, leading to IR drop and overheating.
Tom Williams, Synopsys Fellow

Perspective: How to Improve Design TTR

John Chilton, senior vice president of Marketing and Business Development at Synopsys, talks about the importance of utilizing today’s widely-available multi-core processor-based compute infrastructures to accelerate design TTR.
John Chilton, senior vice president of Marketing and Business Development at Synopsys

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