Enhanced Extraction Solution for Targeted Applications
The StarRC extraction solution suite is available in three different configurations: StarRC Custom, StarRC, and StarRC Ultra. StarRC Custom offers extraction for high-accuracy custom AMS/digital design, StarRC offers full-chip gate-level and transistor-level extraction, and StarRC Ultra offers high-end extraction for advanced analysis flows.
||Li-Pen Yuan Introduces Rapid3D Technology
The new Rapid3D technology in StarRC Custom delivers 20x speed improvement in 3D extraction and addresses the growing accuracy and performance challenges for custom AMS, high speed digital, memory and IP designs.
Li-Pen Yuan, senior director of R&D for the Extraction and Rail Analysis products at Synopsys
||Antun Domic Introduces StarRC Custom
StarRC Custom is a parasitic extraction solution for analog mixed-signal (AMS) and custom digital IC design. By combining the gold standard extraction technologies of Star-RCXT™ and Raphael™ NXT into a single, unified extraction solution, the StarRC Custom solution offers high performance runtime with tuned accuracy to meet the analysis demands of high-sensitivity custom circuits. StarRC Custom is the foundation for the StarRC extraction suite of products.
Antun Domic, senior vice president and general manager of Synopsys’ Implementation Group
StarRC is the EDA industry’s gold standard for parasitic extraction. A key component of Synopsys Galaxy Implementation Platform, it provides a silicon-accurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal (AMS) and memory IC designs. StarRC offers modeling of advanced physical effects needed for leading-edge process technologies, including 28-nm. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows delivers unmatched ease-of-use and productivity to speed design closure and signoff verification. StarRC Ultra offers high-end extraction for advanced analysis flows.
StarRC offers flexible product configurations for specific design applications
- Product Information
- White Papers
- FinFET Process Modeling and Extraction at 16-nm and Below
- Double Patterning Ready Extraction and Signoff: TSMC and Synopsys Update
- Double Patterning Ready Extraction and Signoff: TSMC - Simplified Mandarin
- Double Patterning Ready Extraction and Signoff: TSMC - Traditional Mandarin
- Press Releases