Webinars 

STMicroelectronics Sees Smarter, Faster Sign-off Cycles with Latest StarRC
STMicroelectronics will share their experiences with performance and efficiency advantages seen with the latest releases of StarRC and how they are helping ST to roll out their own products.
Raphael Gras, Sr. Digital Sign-off CAD Engineer, STMicroelectronics
Jun 23, 2016
 
Synopsys and ARM Experts Review Smart Constraint Management Practices for Efficient Timing Closure (Simplified Chinese)
Join Synopsys and ARM to learn more about accelerating timing closure by implementing timing constraint best practices.
James Chuang, Technical Marketing Manager, Synopsys
May 26, 2016
 
Synopsys and ARM Experts Review Smart Constraint Management Practices for Efficient Timing Closure (Traditional Chinese)
Join Synopsys and ARM to learn more about accelerating timing closure by implementing timing constraint best practices.
James Chuang, Technical Marketing Manager, Synopsys
May 26, 2016
 
Synopsys and ARM Experts Review Smart Constraint Management Practices for Efficient Timing Closure
Join Synopsys and ARM to learn more about accelerating timing closure by implementing timing constraint best practices.
Ramnath Swamy , Principal Engineer, ARM Ayhan Mutlu, Principal Engineer, Synopsys
May 25, 2016
 
Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate Early Stage Dynamic Analysis
In this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.
Jack Ting, CAE, Synopsys; Manoz Palaparthi, Technical Marketing Manager, Synopsys
Feb 24, 2016
 
Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate Early Stage Dynamic Analysis (Traditional Chinese)
In this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.
Martin Liu, CAD Engineer, Sunplus Technology
Feb 24, 2016
 
Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate Early Stage Dynamic Analysis (Simplified Chinese)
In this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.
Martin Liu, CAD Engineer, Sunplus Technology
Feb 24, 2016
 
Synopsys Mixed-Signal IP Designers Achieve Increased Productivity Using Enhanced StarRC Netlist Reduction
Learn about StarRC's recent enhancements in RC netlist reduction & how these improvements are helping Synopsys IP developers verify the performance & integrity of their industry-leading IP portfolio.
Sunderarajan S. Mohan, Architect, Analog and Mixed Signal Circuits, Synopsys; Changli Guo, R&D Manager for Extraction Products, Synopsys
Jan 27, 2016
 
Tackle the Complexities of FinFET Library Characterization with SiliconSmart
This webinar will cover the new, innovative SiliconSmart capabilities that will enable you to work smarter in solving your toughest FinFET library characterization challenges.
Ed Lechner, Director of Marketing, Design Analysis and Sign-off Tools, Synopsys
Jan 13, 2016
 
PrimeTime POCV FinFET Designs - the NVIDIA Experience (Simplified Chinese)
Synopsys will review the PrimeTime POCV technology that helps designers reduce design margins in FinFET designs, and you will learn about NVIDIA’s latest FinFET tapeout experience with PrimeTime POCV.
James Chuang, Senior Technical Marketing Manager, Synopsys
Nov 17, 2015
 
PrimeTime POCV FinFET Designs - the NVIDIA Experience (Traditional Chinese)
Synopsys will review the PrimeTime POCV technology that helps designers reduce design margins in FinFET designs, and you will learn about NVIDIA’s latest FinFET tapeout experience with PrimeTime POCV.
James Chuang, Senior Technical Marketing Manager, Synopsys
Nov 17, 2015
 
Enabling Automotive IC Design Reliability
In this webinar, we introduce the challenges facing of designers of high-reliability ICs for the automotive market, and discuss some of the proven Galaxy Design Platform IC implementation and sign-off solutions being deployed by automotive design teams worldwide.
Steve Smith, Senior Director of Marketing, Automotive Solutions
Nov 12, 2015
 
High Performance, High Accuracy Clock Inductance Extraction with StarRC
Learn how inductance impacts high-frequency design performance, and how StarRC’s new clock net inductance extraction feature has been specifically designed to model this new parasitic effect.
Krishna Sundaresan, Corporate Applications Engineer Director, Synopsys, Inc.
Oct 15, 2015
 
STMicroelectronics’ Experience: Synopsys Logic BIST for Automotive and Safety-Critical Designs
ICs targeted for safety-critical applications must be able to perform in-system self-test in compliance with functional safety standards such as ISO 26262. In this webinar, Synopsys highlights synthesis-based logic BIST that addresses the self-test requirements for safety-critical designs. Our guest speaker from STMicroelectronics presents results and details of Synopsys’ test solution successfully deployed on production designs.
Cinzia Bartolommei, Senior DFT Engineer, STMicroelectronics; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Jul 30, 2015
 
STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95%
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
Sebastien Marchal, Principal Engineer, STMicroelectronics; Stephan Mahnke, Staff Corporate Applications Engineer, Synopsys
Jul 29, 2015
 
STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95% - Traditional Chinese
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
James Chuang, Senior Technical Marketing Manager, Synopsys
Jul 29, 2015
 
STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95% - Simplified Chinese
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
James Chuang, Senior Technical Marketing Manager, Synopsys
Jul 29, 2015
 
Qualcomm Achieves Significantly Faster TAT with StarRC Ultra-scalable SMC Solution
Qualcomm and Synopsys will discuss the latest productivity features inside StarRC that enabled Qualcomm to achieve significant speedup in extraction and faster design closure.
Khusro Sajid, Sr. Staff Engineer, Qualcomm; Arindam Chatterjee, Manager, R&D, Synopsys;
Apr 28, 2015
 
Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO – with Samsung case study
Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.
Synopsys
Apr 22, 2015
 


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