The Synopsys PrimeTime SIG is an active community for all PrimeTime users and design engineers who want to stay connected with the latest developments in the field of Static Timing Analysis (STA).
PrimeTime SIG 2010 – Silicon Valley
A PrimeTime SIG event was held in Sunnyvale, CA on Wednesday, October 27, 2010.
PrimeTime users and managers attended the event from the top semiconductor companies. The subject of this SIG was Deploying HyperScale Technology for Faster Timing Analysis.
Customer presentations are available for download from SolvNet.
Sr. VP and GM, Implementation Group, Synopsys
Antun kicked off the SIG event highlighting PrimeTime achievements in the recent past and introduced the new HyperScale technology.
Member of Technical Staff, SoC Design Methodology, AMD
Kent touched upon AMD’s need for HyperScale due to the ever growing design sizes and complexity and heavy IP reuse and how the HyperScale flow will enable timing convergence faster and improve their productivity.
Technical Lead, Cisco
KH provided insight into the different phases of the Cisco STA flow and how he can take advantage of HyperScale by reducing the number of iterations he has to do today.
Physical Design Lead, NVIDIA
Richard highlighted the significant runtime and memory advantages of HyperScale and how it will help NVIDIA’s large designs with faster and smaller STA runs.
Sr. R&D Manager, Synopsys
Patrick delved into how HyperScale works and shared the latest runtime, memory and accuracy results.
The event was held during lunch during which the attendees had the opportunity to talk with industry peers and PrimeTime R&D.
Antun Domic, Sr. VP and GM, Implementation Group, Synopsys
Kent Dozier, Member of Technical Staff, SoC Design Methodology, AMD
K.H. Kim, Technical Lead, Cisco
Richard Yuan, Physical Design Lead, NVIDIA
Presenters & Synopsys R&D: Ken Rousseau, VP Engineering, Patrick Fortner, Sr. R&D Manager, Ahsan Bootehsaz, VP Engineering
PrimeTime HyperScale Technology