PrimeTime 

Golden Signoff Solution 

The Synopsys PrimeTime suite provides a single, golden, trusted signoff solution for timing, signal integrity, power and variation-aware analysis. It delivers HSPICE® accurate signoff analysis that helps pinpoint problems prior to tapeout thereby reducing risk, ensuring design integrity, and lowering the cost of design. This industry gold-standard improves your team’s productivity by delivering fast turnaround to shave precious time from development schedules for large and small designs while ensuring first-pass silicon success through greater predictability and the highest accuracy.

 

The Synopsys PrimeTime suite includes PrimeTime, PrimeTime SI, PrimeTime ADV, PrimeTime GCA, PrimeTime PX and PrimeTime VX. Anchored by the most trusted and advanced static timing signoff solution for gate-level designs, the PrimeTime suite offers comprehensive signal integrity analysis, statistical timing analysis, timing constraint analysis and full chip power analysis in a single integrated environment.

Key Benefits:
  • HSPICE-Accurate Results Minimize Over-Design
  • Integrated Design Environment Improves Productivity
  • Fast Turn-around Time Speeds Analysis and Signoff
  • High Capacity Approach Reduces Hardware Costs
  • Complete Solution Ensures Comprehensive Signoff
  • Multi-scenario ECO Accelerates Timing Closure and Leakage Recovery
  • Fast, Flexible, Timing Constraint Analysis
  • Accurate Analysis of Latch-Based Designs
  • Latest On-Chip Variation Modeling Technology Accelerates Timing Signoff

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ECO Guidance
PrimeTime ECO Guidance technology uses signoff-driven analysis to efficiently identify ECO changes for DRC and timing fixes at block or chip level, shortening tape-out schedules by weeks. Multi-scenario enabled physical-aware ECO guidance reduces the time and iterations required to reach timing closure on congested designs. In addition, PrimeTime ECO Guidance can take advantage of positive timing slack to identify leakage power reduction opportunities.

HyperScale
PrimeTime HyperScale technology extends PrimeTime static timing analysis to support designs beyond 500 million instances. It delivers between 5 and 10X better runtimes for the full chip timing analysis and 5 to 10X smaller memory footprint compared with classic flat analysis. PrimeTime HyperScale technology enables hierarchical STA by performing accurate block level timing analysis in the top-level context. This offers faster top and block timing convergence, and offers scalability to complete daily analysis on designs of 500M instances and beyond. 5-10X boosts in performance and capacity allow design teams to make more effective use of existing hardware resources.

On-Chip Variation
As on-chip variation (OCV) effects continue to increase with shrinking geometry nodes, applying a flat global margin across the entire chip can lead to overdesign, reduced design performance, and longer timing closure cycles. The PrimeTime Advanced OCV solution takes advantage of improved device-level variation modeling techniques to provide the right balance between accuracy and performance.

Multi-scenario Analysis
PrimeTime offers a number of technologies to accelerate both the analysis and debug of multi-scenario designs. Going beyond multi-scenario analysis, PrimeTime mode merging and simultaneous multi-voltage aware analysis (SMVA) actively work to reduce the number of scenarios to be analyzed. This allows users to reduce the hardware resources and turnaround time for multi-scenario analysis, while maintaining signoff quality timing correlation. Distributed Multi-Scenario Analysis (DMSA) and Interactive Multi-Scenario Analysis (IMSA) allow users to efficiently setup and debug multi-scenario runs.

Timing Constraint Analysis
The rapid increase in design size and complexity, as well as the widespread reuse of IP design blocks, has led to a major increase in the size and complexity of timing constraint specification files. Ensuring high-quality timing constraints is paramount to efficient design implementation, especially during handoffs between teams. Incomplete, inconsistent or conflicting constraints can cause optimization and implementation tools to run ineffectively or to never converge. To address this challenge, PrimeTime GCA provides a comprehensive set of rule checks designed to maximize the efficiency of implementation and timing analysis.

What is the PrimeTime Special Interest Group (SIG)?
The Synopsys PrimeTime Special Interest Group (SIG) is an active community for all PrimeTime users and design engineers who want to stay connected with the latest developments in the field of Static Timing Analysis (STA). Increasing design size and complexity are putting tremendous pressure on design schedules. STA is a key technology used throughout the design process to accelerate design closure. As STA technology rapidly evolves, the PrimeTime SIG helps design teams stay abreast of the latest developments to help maximize their effectiveness and throughput.

PrimeTime SIG 2014 Events

PrimeTime SIG at SNUG India 2014
Accelerating Timing Closure with Advanced Technologies
June 25, 2014 Reception

Primetime SIG at DAC 2014
Accelerating Timing Closure with Advanced Technologies
June 2, 2014 Dinner

PrimeTime SIG 2013 Events

PrimeTime SIG at SNUG Japan 2013
Advanced ECO Methodology
July 12, 2013 Lunch

PrimeTime SIG at SNUG India 2013
Advanced ECO Methodology
June 12, 2013 Dinner

PrimeTime SIG at DAC 2013
Technology Panel: Advanced ECO Methodology
June 3, 2013, Dinner and Music

PrimeTime SIG at SNUG Silicon Valley
Topic: PrimeTime ADV - Advanced Timing Technology
March 26, 2013 Dinner

PrimeTime SIG Events Archive

PrimeTime 2014 Webinar Series

On-Demand
Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow
Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16 nm technology node and its impact to extraction and timing analysis. Learn about the latest developments in StarRC and PrimeTime that are V1.0 certified by TSMC to signoff your 16 nm designs.
English | Simplified Chinese | Traditional Chinese

PrimeTime 2013 Webinar Series

On-Demand
Fastest Multi-scenario Timing Closure with PrimeTime Physically-aware ECO – AMD Shares Results
AMD and Synopsys will discuss the latest enhancements to PrimeTime's ECO Guidance technology to accelerate multi-scenario timing closure.
English | Simplified Chinese | Traditional Chinese

GLOBALFOUNDRIES / Synopsys Share Signoff Best Practices
This webinar will outline the essential elements of an effective advanced node signoff flow with PrimeTime and StarRC.
English | Simplified Chinese | Traditional Chinese

Reducing Multi-mode STA Turnaround Time with PrimeTime Mode Merging - LSI Case Study
This webinar will introduce new PrimeTime technology to help design teams manage scenario increases by merging modes. LSI will discuss how PrimeTime mode merging allows them to reduce timing analysis.

PrimeTime 2012 Webinar Series

On-Demand
利用PrimeTime Advanced OCV减少设计馀量 - Simplified Mandarin
学习芯片设计工程师如何利用PrimeTime Advanced OCV消除过度悲观的违例并加速设计收敛, 以及晶圆代工厂对这些新科技的看法和支持模式.

利用PrimeTime Advanced OCV減少設計餘量- Traditional Mandarin
學習晶片設計工程師如何利用PrimeTime Advanced OCV 消除過度悲觀的Violation以加速設計收斂, 以及晶圓代工廠對這些新科技的看法和支援模式.

Accurate Early Stage Power Estimation with PrimeTime PX: The NVIDIA Experience
In this webinar we will review the need for early power analysis, and show how useful power estimates can be achieved even with early and/or incomplete data. NVIDIA will outline their strategies.

网上活动: 利用PrimeTime节省数周ECO修复的时间
研讨芯片研发设计团队如何在综合与验收阶段节省数周的时间. 学习如何利用PrimeTime新世代的ECO导引功能自动化修复DRC, 建立时间, 与保持时间的违例, 进而缩减设计流程的迭代并缩短ECO修复所须的时间.

網上活動: 利用PrimeTime節省數週ECO的時間
研討晶片研發設計團隊如何在Implementation與Sign-off階段節省數週的時間. 學習如何利用PrimeTime新世代的ECO導引功能自動化修復DRC, Setup, 與Hold Violation, 進而縮減設計流程的Iteration並縮短ECO Fixing所須的時間.

5X Faster PrimeTime Multivoltage Timing Signoff: A Renesas Case Study
Learn how PrimeTime's new multivoltage aware analysis technology reduces risk and speeds signoff for designs with multiple voltage domains, and how Renesas has successfully deployed it to reduce signoff turnaround time by 5X.

Faster PrimeTime Signoff - Tips, Tricks and New Technology
Learn how to achieve a 2X reduction in signoff TAT, and build the expertise to create high-performance signoff scripts.

Streamlining Your ECO Flow For Fastest Setup, Hold and Timing DRC Closure
Learn what's new with timing-aware DRC guidance for ECOs and which design flow and tool settings provide the fastest timing closure at 28 nm and below.

PrimeTime 2011 - 2010 Webinar Series

Access PrimeTime GCA Features During Timing Analysis

Access PrimeTime GCA Features During Timing AnalysisLearn how PrimeTime GCA can be used to analyze constraint errors during timing analysis
Runtime: 2:20 min.  Share This


Fixing ECOs with PrimeTime

Fixing ECOs with PrimeTimeLearn how PrimeTime ECO can save you weeks of effort in timing closure with multi-scenario ECO fixing, and how PrimeTime can reduce the complexity of multi-scenario analysis by providing instant visibility to all scenarios in a single view.
Runtime: 7:53 min.  Share This


Faster Debug: Filter-driven Schematic Highlighting

Faster Debug: Filter-driven Schematic HighlightingLearn the most effective way to find objects in PrimeTime schematics.
Runtime: 2:24 min.  Share This


Faster Debug: The PrimeTime Path Analyzer

Faster Debug: The PrimeTime Path AnalyzerSee how the Path Analyzer can be used to quickly review and categorize large numbers of timing paths.
Runtime: 3:39 min.  Share This


Faster Debug: Selective Schematic Abstraction

Faster Debug: Selective Schematic AbstractionLearn how to easily reduce complexity and accelerate debug with the PrimeTime schematic.
Runtime: 2:05 min.  Share This


Simultaneous Multi-Voltage Aware Timing Analysis

Understand how PrimeTime's Simultaneous Multi-Voltage Aware (SMVA) Analysis helps you avoid the accuracy and runtime compromises normally associated with timing signoff of multi-voltage designs.
Runtime: 10:41 min.  Share This

Debugging Clock Problems with PrimeTime SI

Explore the options available in PrimeTime SI to identify and debug clock issues that can prevent timing closure.
Runtime: 8:36 min.  Share This

Clock Constraint Analysis with Galaxy Constraint Analyzer

See how you can easily get up and running with Galaxy Constraint Analyzer, and quickly identify critical clock constraint problems that could put your signoff at risk.
Runtime: 10:16 min.  Share This

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