PrimeTime Special Interest Group (SIG) at DATE 2012 

The Synopsys PrimeTime SIG is an active community for all PrimeTime users and design engineers who want to stay connected with the latest developments in the field of Static Timing Analysis (STA).

Co-sponsored by Global Foundries

PrimeTime SIG at DATE 2012

A PrimeTime Special Interest Group (SIG) event on Gigascale design signoff featuring Advanced OCV, PrimeTime ECO, and HyperScale technology was held at DATE in Dresden, Germany, on Tuesday, March 13, 2012. The event was held over lunch where PrimeTime users and managers from semiconductor companies had the opportunity to talk with industry peers and PrimeTime R&D.

Customer presentations are available for download from SolvNet.

Speakers

Dr. Antun Domic
Senior Vice President and General Manager, Implementation Group
Synopsys, Inc.

Antun Domic kicked off the event and welcomed the audience. He described the Gigascale design challenges for timing signoff and the evolution of PrimeTime over the recent releases to address these challenges. He also gave a preview of exciting PrimeTime technologies coming up in 2012 and 2013.


Robert Madge
Director, Design Enabled Manufacturing
GLOBALFOUNDRIES, Inc.

Robert, the session chair, highlighted the technical collaboration between Synopsys and GLOBALFOUNDRIES and introduced the speakers of the event.


Rainer Mann
Staff Engineer
GLOBALFOUNDRIES, Inc.

Rainer presented the key PrimeTime technologies as part of the GLOBALFOUNDRIES reference flow at 28 nm and also 20 nm for assuring silicon success. The key pieces include composite current source (CCS), distributed multi-scenario analysis (DMSA), PrimeTime ECO, and advanced on-chip variation (AOCV).


Rob Aitken
R&D Fellow
ARM, Ltd.

Rob Aitken detailed their experience on generating AOCV tables and timing closure with PT ECO on ARM cores. He also shared how PrimeTime ECO helped them converge faster on a high-performance Cortex A15 processor.


Pierre Gazull
CAD Senior Engineer
STMicroelectronics

Pierre focused on their deployment experience with PrimeTime ECO on a 32-nm SoC chip that recently taped out. He showed the results on a multivoltage design with over 90% fixing rates of setup and hold violations after place and route, which saved them precious turnaround time.


Steve Hollands
Senior R&D Manager, PrimeTime
Synopsys, Inc.

Steve reviewed what Gigascale signoff design challenges may exist, their impact, and how to address them.


Antun Domic describing Gigascale design challenges.


Robert Madge highlighting technical collaboration.

Rainer Mann Rainer presenting key PrimeTime technologies as part of the GLOBALFOUNDRIES reference flow at 28 nm and 20 nm.


Rob Aitken detailed their experience on generating AOCV tables

Pierre Gazull focused on their deployment experience with PrimeTime ECO on a 32-nm SoC chip.


Steve Hollands reviewed Gigascale signoff design challenges.



NewsArticlesWhite PapersWebinarsVideos