PrimeTime 2011 Webinar Series
Faster Clock Analysis and Debug
Analyze clock constraints sooner, identify problems quicker, and debug timing violations faster. Learn how to save time using Galaxy Constraint Analyzer and PrimeTime to ensure clean clock constraints and keep clocks free of timing violations during signoff.
Save Weeks Fixing ECOs with PrimeTime and IC Compiler
See how design teams are saving weeks during implementation and signoff. Learn how PrimeTime Next-Generation ECO guidance and IC Compiler automatically fix DRC, setup and hold violations to reduce it.
Fast Timing Constraint Cleanup with Galaxy Constraint Analyzer
This technical webinar will explain how Galaxy Constraint Analyzer helps to produce signoff-quality timing constraints quickly, for even the most complex designs.
Debug Timing Faster with PrimeTime Visualization Tools
Save time debugging complex timing paths during implementation and signoff using new visualization techniques in PrimeTime. See new clock and data analysis capabilities in action.
Reducing Design Margins Using PrimeTime Advanced OCV - TSMC and User Views
Learn how designers are using PrimeTime Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about TSMC's views and support model for these new technologies.
PrimeTime 2010 Webinar Series
Performing Accurate Power Analysis on Low Power Designs Using PrimeTime PX
Learn how to analyze the effectiveness of low power techniques in your design, which modes of operation consume the most power, and how to deploy PrimeTime PX to optimize your design to meet low power requirements.
Faster ECO Fixing Flows with PrimeTime and IC Compiler
Learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively using Distributed Multi-Scenario Analysis for automatic set-up, hold and DRC fixing.
Reducing Design Margins Using PrimeTime Advanced OCV
Explains how Advanced On-Chip-Variation works in comparison to flat-derate OCV and statistical STA-based signoff technologies, and will contrast the cost of adoption and accuracy of these three methods.
Addressing Signal Integrity Noise in Low Power Design
Discusses the impact of low power design and the resulting requirements that drive the technologies in today's static timing analysis tools.