How To Extend Litho Scaling
Given the industry’s track record of technology development, it’s likely that lithographic techniques will be extended with new innovations.
Feb 19, 2015

Yield Ramp Challenges Increase
As the industry moves down process nodes, it is increasingly difficult to ramp yield from both a test and manufacturing perspective. What is the next step?
Dec 11, 2014

Photoresist Problems Ahead
As the semiconductor industry begins its ramp to manufacturing at 10nm and below, activity is heating up involving lithography modeling. The goal is to be ready when all the pieces of the puzzle are in place. That includes EUV, when it finally becomes commercially viable, as well as extending ArF Lithography.
Nov 17, 2014

OPC Modeling Game Changer: Rigorously-tuned Compact Modeling
Model-based optical proximity correction (OPC) has been an effective application to help achieve design intent in the lithographic process since the late 1990’s with the introduction of the 180 nanometer (nm) technology nodes, but with continued push of the current ArF immersion imaging hardware into the sub-20nm nodes, traditional OPC modeling approaches are struggling to keep pace. The quality of the OPC results is dependent on the accuracy and predictability of the model, which is heavily reliant on the input metrology data and physicality of the model terms.
Nov 13, 2014

Faster Yield Ramp at Sub-100-nm Technologies Using Design-Centric Volume Diagnostics Approach
At process nodes below 100 nanometers (nm), achieving yield ramp becomes both more critical and a greater challenge for semiconductor manufacturers. New manufacturing steps, materials and device types, coupled with escalating process variations and a host of other challenges, continually increase the difficulty in device scaling.
Oct 27, 2010

Accurate EUV lithography simulation enabled by calibrated physical resist models
This article assess the readiness of rigorous physical resist model calibration for accurate EUV lithography (EUVL) simulation -- first, summarizing the experimental setup for the EUVL and discussing pattern selection for calibration, then illustrating the speed and robustness of model building, which allows overnight determination of accurate models.
Sep 13, 2010

Yield Metrology Looking at Systematic Failure
Sagar Kekare of Synopsys discusses his paper on rapid root cause analysis and process change validation using design-centric volume diagnostics in a video interview with Debra Vogler of Solid State Technology.
Jul 14, 2010

EDN: Design-centric yield management
In the race to the market, IC vendors have few avenues remaining to claim the first-to-market advantage.
Mar 12, 2009

EDN: Synopsys tries to organize its efforts in EDA multiprocessing
It’s hard to imagine a set of applications that need computing resources more than the chain of EDA tools for a 65 nm chip design. (OK, searching for extraterrestrials, maybe, but the economics are a bit different there.)
Mar 10, 2008