Videos 


DAC 2016 Custom Compiler Lunch Videolog: Cutting Layout Tasks from Days to Hours

FinFET devices have added significant complexity to the design flow, and many companies are seeking new solutions for custom design. Custom Compiler’s pioneering visually-assisted automation can cut layout tasks from days to hours.

On June 7, 2016, Synopsys hosted a Custom Compiler Luncheon at DAC. At this event, attendees heard users discuss their experiences with custom design challenges and how they have deployed Custom Compiler to improve their custom design productivity for both FinFET and established nodes.
GSI, Samsung, STMicroelectronics, Synopsys IP



DAC 2016 Circuit Simulation Lunch Videolog: Robust AMS Design Verification at Advanced Nodes

On June 6, 2016, Synopsys hosted a Circuit Simulation Luncheon at DAC. At this event, attendees heard Industry leaders from Oracle, Samsung and STMicroelectronics discuss their design verification challenges that stem from cutting-edge advanced technologies and increasing design complexity in memory, analog, and mixed-signal applications, and how they overcome such challenges by using Synopsys AMS circuit simulation solutions to ensure design robustness.
Sam Lo, Hardware Development Manager, Oracle; Zach Coombes, CAD Engineer, Samsung; Atul Bhargava, Sr. Staff Engineer, STMicroelectronics



IC Compiler II - Achieving Industry-Best QoR on Advanced Designs

In this video, hear from industry leaders about how they are achieving success in their advanced designs using IC Compiler II technology to address physical design challenges and accelerate products to market.
HiSilicon, NVIDIA, Qualcomm, Socionext



SNUG 2016 Custom Compiler Videolog: Cutting Layout Tasks from Days to Hours

On March 31, 2016, Synopsys hosted a Custom Compiler Lunch ‘n’ Learn at SNUG Silicon Valley. At this event, attendees heard industry leaders share their experiences using the new Custom Compiler visually-assisted automation to meet the challenges of FinFET custom design, and discuss how it improves their custom design productivity.
AMD, STMicroelectronics, Synopsys IP



Introducing Custom Compiler Visually-assisted Automation

Antun Domic, Executive VP and GM of the Design Group unveils Synopsys' next-generation custom design solution.

Custom Compiler brings new levels of productivity to FinFET layout by employing visually-assisted automation technologies that speed up common design tasks, reduce iterations, and enable reuse.
Antun Domic, Executive VP and GM of the Design Group, Synopsys



Accelerating SoCs to Market with the Power of 10X

IC Compiler II has proven to be a game-changer in physical design, accelerating silicon success for designers of the world's most advanced ICs. Hear industry leaders discuss how 10X faster throughput has transformed the way they think about product development, opening up a world of new opportunities.
AMD, ARM, MediaTek, Samsung, Socionext



IC Compiler II - Accelerating Products to Market with the Power of 10X

On March 23, 2015, during the 25th annual Synopsys User Group (SNUG) in Silicon Valley, industry leaders shared how 10X faster throughput has transformed the way they think about product development, opening up a world of new opportunities. Watch this video to learn why, just one year after its introduction, IC Compiler II has proven to be a game-changer in physical design.
ARM, MediaTek , Renesas, Synopsys, Toshiba



In-Design Physical Verification Milestone

In this video, Synopsys Chairman and CEO, Dr. Aart de Geus shares his view on the broad and rapid adoption of this new technology and how it could change physical verification going forward.
Dr. Aart de Geus, Synopsys Chairman and CEO



Get the Best Performance from PrimeTime

Karen Linser, staff applications engineer in Synopsys’ Implementation Group, describes a few easy ways for getting the best PrimeTime performance and achieving faster sign-off analysis.
Karen Linser

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10X Faster Routing Runtime

Combine advanced routing algorithms with multi-threading technology, and you get a speed increase of >10X on quad-core machines.
Tong Gao, Synopsys Scientist and architect of Zroute


A System Level Design Strategy

The Electronics Technology Channel Unifying or Overrated: A System Level Design Strategy
Joachim Kunkel, Synopsys inc.



Perspective: Boost your design productivity

Design Compiler Graphical, the newest member of the Design Compiler product family, creates a better starting point for physical implementation and can shave weeks off your design schedule.
Antun Domic, senior vice president and general manager of Synopsys' Implementation Group



Small Delay Defects-The Need for Better At-Speed Tests

Manufacturing process variations can introduce small delays that adversely affect critical design paths, leading to circuit failures. Dr. T.W. Williams introduces technology developed at Synopsys to detect defects creating these delays, thereby increasing the test quality.
Tom Williams, Synopsys Fellow



Perspective: How to Improve Design TTR

John Chilton, senior vice president of Marketing and Business Development at Synopsys, talks about the importance of utilizing today’s widely-available multi-core processor-based compute infrastructures to accelerate design TTR.
John Chilton, senior vice president of Marketing and Business Development at Synopsys