Transaction-Level Models
The Synopsys DesignWare® System-Level Library provides product development teams a comprehensive set of standards-based, tool-independent transaction-level models (TLMs) that serve as the building blocks of virtual platforms. Virtual platforms are fully functional software models of complete embedded systems, enabling pre-silicon software development and software-driven system validation. The ability to parallelize the hardware and software development effort through virtual platforms significantly reduces the product design cycle and speeds time to market.
The OSCI TLM-2.0-compliant models in the System-Level Library are written in SystemC™ to function with any IEEE 1666-compliant SystemC simulator. Mirroring the productivity gains realized by IP reuse in the implementation phase, the System-Level Library accelerates the development of virtual platforms by providing pre-defined abstract models of hardware components in wireless, multimedia, networking and automotive application domains.
Download Complete DesignWare System-Level Library Datasheet
Download SuperSpeed USB 3.0 Transaction-Level Models Datasheet
- Highlights
- Production-proven transaction-level models (TLM's), including:
- High performance processor models
- Synopsys DesignWare Cores models
- Synopsys DesignWare AMBA component models
- ARM PrimeCell models
- Infrastructure models
- Pre-assembled platforms assembled from transaction-level models that serve both as demo vehicles as well as starting points for new virtual platform development
- Written in SystemC to run with any IEEE 1666-compliant SystemC simulator
- TLM-2.0 compliant
- Model Authoring Kits to accelerate the development of customer-specific models by providing software building blocks.
Transaction-level models that are currently available in the DesignWare System-Level Library include:
- Processor Models
Loosely timed (LT, also known as programmer’s view, PV): - ARM7TDMI
- ARM920T
- ARM926EJ-S
- ARM946E-S
- ARM1136JF-S
- ARM1176JZF-S
- MIPS4Kc
- IBM PowerPC 405, 440, 460
- Processor Model Adapters
Enabling easy plug-in of vendor-supplied ISS models - TLM-2.0 bridge for Tensilica Xtensa
| - DesignWare Interface IP
Loosely timed (LT) - SuperSpeed USB 3.0 Host
- SuperSpeed USB 3.0 Device
- USB 2.0 Host
- USB 2.0 OTG Host/Device
- SATA Host
- SATA AHCI
- Ethernet 10/100/1G
- PCIe (endpoint / root complex)
- DesignWare AMBA Models
Loosely timed (LT) - Interconnect matrix (AXI, AHB, APB)
- Memory (DMA controller, generic models)
- Interrupt controller, timer, UART, etc.
| - ARM Prime Cells Models
Loosely timed (LT) - DMAC
- Interrupt Controller
- UART
- Dual timer
- Watchdog
- Interprocessor Control
- Synchronous Serial port
- General-Purpose I/O
- Real-time clock
- Peripheral models
Loosely timed (LT) - HTS27210 SATA Hard Drive
- USB 3300 OTG PHY
- USB 2.0 nanoPHY
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- Generic Models (LT)
- coreManager (clock and reset manager)
- Interrupt controller
- Generic Ethernet PHY
- Tester
- ComponentStub, I2C
- Component Stub, register
- RAM / smartRAM
- UART
- Initialization
- Infrastructure models (LT)
- AddrBias
- AddrMux
- MemoryDecoder
- PinStub
- Nb_transport Stub
- User I/O Models (LT)
- TLM-2.0 monitor
- RegisterVieW
- VT100
- File-IO
- InterfaceSpy
- muxRoutingView
- PowerDashboard
| - Model Authoring Kits
Loosely timed (LT) - Pre-Assembled Platforms
Loosely timed (LT) - VPAI: ARM integrator platform
- VPTEST: generic test platforms, for all DesignWare Interface IP models
- VPQSML: quick-start multi layer
- VPMP: multi-media player demo
| - Processor Models
Cycle Accurate (CA) - DesignWare AMBA Models
Cycle Accurate (CA) - Bus models (AHB, APB, arbiter, decoder, etc.)
- Memory support (DMA controller, ROM, RAM, memory monitor, etc.)
- TLM-to-PIN adapters
- IBM Core Connect Models
Cycle Accurate (CA) - Bus models (PLB, PCIX, OPB, DCR)
- Memory support (DMA controller, DDR2 memory controller , etc.)
- Interrupt controller, UART, etc.
- Master /slave model templates
- Pre-Assembled Platforms
Cycle-accurate (CA) - examples featuring AMBA and CoreConnect configurations
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