|Extending Digital Verification Techniques for Mixed-Signal SoCs with VCS AMS|
The VCS AMS mixed-signal verification solution extends proven digital verification techniques to mixed-signal designs to deliver high-quality verification coverage of complex mixed-signal SoCs.
Helene Thibieroz, Adiel Khan, Dave Cronauer, Synopsys
|Custom and Mixed-Signal Design Solution|
Synopsys’ unified solution for custom and cell-based design and verification provides a comprehensive, highly integrated suite of tools for advanced-node mixed-signal SoC design. The high degree of integration and interoperability shortens time-to-tapeout and improves design quality.
|Understand and Avoid Electromigration (EM) & IR-drop in Custom IP Blocks|
This whitepaper discusses the various trends exacerbating EM and IR-drop effects as well as design and analysis techniques to avoid them, and introduce Synopsys’ transistor-level analysis solution, which includes CustomSim for FastSPICE circuit simulation, StarRC for extraction, and Galaxy Custom Designer for custom layout.
Bradley Geden, Solutions Architect, Synopsys
|MOS Device Aging Analysis with HSPICE and CustomSim|
MOS Reliability Analysis (MOSRA) in HSPICE and CustomSim offers a robust and economic alternative
to empirical overdesign and extensive lifetime testing.
Bogdan Tudor, Joddy Wang, Weidong Liu, Hany Elhak, Synopsys
|Using Digital Verification Techniques on Mixed-signal SoCs with CustomSim and VCS|
A case study that explains the various aspects of a scalable and reusable methodology for verifying analog IP that can be applied to VMM/UVM, from verification planning to testbench implementation and coverage collection.
Graeme Nunn, Calvatec; Fabien Delguste, Adiel Khan, Abhisek Verma, Bradley Geden, Synopsys
|Automated Regression for Mixed-Signal Verification|
CustomExplorer™ Ultra represents the next generation in mixed-signal verification environment, including regression management, debug and analysis for complex SoC design.
Duncan McDonald, Product Marketing Manager, Synopsys
|De-risking Variation-aware Custom IC Design with Solido Variation Designer and Synopsys HSPICE|
Challenges in a traditional custom IC variation-aware design flow lead to schedule, product yield, and product quality risks. Solido Variation Designer and Synopsys HSPICE together enable fast and accurate variation-aware design methods that can reduce or remove risks associated with traditional variation-aware design. Together, these tools and methods help to reliably deliver products on schedule that are competitive and cost-effective.
Jeff Dyck, Director of Product Development, Solido Design Automation, Inc.; Kishore Singhal, Scientist, Synopsys
|IC Validator: Physical Verification for Analog Designs|
Physical verification challenges of analog designs are different than the challenges of large digital designs. In addition to complex runset requirements, a tight interface to a parasitic extraction tool and an easy-to-use GUI are needed to use a runset effectively in an analog design environment. IC Validator, the latest generation physical verification tool, can be used to solve these issues. This paper addresses many of the physical verification requirements of analog designers and how they are met with IC Validator.
Al Blais, Global Technology Services, Synopsys
|Accelerating Analog Simulation with HSPICE Precision Parallel Technology|
HSPICE Precision Parallel technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SERDES, and other full mixed-signal circuits. HPP addresses the traditional bottleneck in accelerating SPICE on multicore CPUs with new algorithms that enable a larger percentage of the simulation to be parallelized, with no compromise in golden HSPICE accuracy. Additionally, efficient memory management allows simulation of
post-layout circuits larger than 10 million elements.
Robert Daniels, Sr. Staff Engineer, Synopsys Inc.; Harald Von Sosen, Principal Engineer, Synopsys Inc.; Hany Elhak, Product Marketing Manager, Synopsys Inc.
|Utilizing Digital Techniques for Analog and Mixed-Signal Verification|
The ability of CustomSim to co-simulate with Synopsys’ VCS digital simulator opens up the possibility of a “best of both worlds” approach enabling the majority of the chip to be simulated in the digital domain while the FastSPICE tool handles the analog blocks. Using this mixed-signal approach, many techniques and philosophies that are common in the digital world can be applied to the verification of mixed-signal systems.
Andy Milne, Application Consultant, Synopsys, Inc.; Damian Roberts, Application Consultant, Synopsys, Inc.
|Extraction Techniques for High-performance, High-capacity Simulation |
Today’s advanced process technologies and faster time-to-market schedules are pushing the limits of verification tools. Post-layout simulation runtimes are increasing 2-4x with every new process generation as chip transistor counts double and new parasitic effects come into play. The Synopsys StarRC™ extraction solution offers a wide range of features to boost the simulation performance and capacity of transistor-level custom digital, analog/mixed-signal and memory designs.
Omar Shah, Corporate Application Engineer; Shekhar Kapoor, Marketing Manager, Synopsys
|StarRC Custom Rapid3D Extraction|
The next-generation Rapid3D technology in StarRC Custom provides an integrated 3D extraction solution to address these
growing accuracy, performance, capacity and ease-of-use needs. This paper presents the new Rapid3D technology and the
benefits it provides for a range of target applications, including IP characterization as well as custom analog/mixed-signal (AMS),
high-speed digital and memory array designs.
Omar Shah CAE, Synopsys Inc. Mathew Koshy R&D Manager, Synopsys Inc.