CustomSim Circuit Check 


CustomSim Circuit Check (CCK) helps users to avoid wasted simulation time by finding design and performance problems automatically, reporting potential problems in a circuit before running simulation. Circuit Check increases verification coverage and discovers potential trouble spots that simulation misses.

Parametric checks
Circuit Check scans the netlist for common geometrical and electrical parameter errors:
  • MOSFET W, L, drain/source area, perimeter, tox
  • User limits can be set for each device model
  • Capacitor values
  • Simulation temperature
Parametric checks
Design and Electrical rule checks
CCK finds hookup and bias errors before simulation:
  • Floating MOSFET gates
  • Forward-biased diodes, bulk nodes
  • No path to Vdd or GND
  • Shorted nodes: PMOS to GND, NMOS to Vdd
During simulation, CCK monitors:
  • Min/max voltages between nodes
  • Excessive element currents
  • Forward-bias conditions

Design and Electrical rule checks
Digital logic/memory diagnostics
CCK prevents time-consuming debug problems:
  • Identifies un-initialized latches before transient simulation
  • Finds stuck-at nodes
  • Reports excessive stack-up of NMOS, PMOS devices
CCK traces logic paths:
  • Interactive debug mode
  • Finds the source of state changes

Digital logic/memory diagnostics
Timing checks
CCK performs static transistor-level timing analysis:
  • Computes Elmore delays
  • Measures rising paths to Vdd, falling paths to GND
Dynamic timing analysis:
  • CCK traces all path delays between source and target nodes

Timing checks
Signal integrity
CCK static crosstalk analysis:
  • Measures delay paths connected to floating parasitic capacitors
  • Calculates potential noise glitch
  • Identifies fast falling paths and slow rising paths

Signal integrity
Low-power design and leakage detection
Find DC leakage:
  • Static check reports any path leaking current between voltage sources
Monitor standby current during simulation:
  • Detects potential leakage paths from multiple power supply domains
  • Identifies high-Z nodes, tests for leakage to GND/Vdd

Low-power design and leakage detection

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