The Synopsys VCS® functional verification solution (Figure 1) is the primary verification solution used by most of the world’s top 20 semiconductor companies. VCS provides the industry’s highest performance simulation and constraint solver engines. In addition, the comprehensive VCS solution offers Native Testbench (NTB) support, broad SystemVerilog support, verification planning, coverage analysis and closure, and native integration with Verdi, the industry’s de-facto debug standard. VCS is uniquely positioned to meet designers’ and verification engineers’ needs to address the challenges and complexity of today’s SoCs.
Industry-leading performance and capacity
- Compile time: Partition compile, Precompiled IP, Dynamic Reconfiguration
- Runtime: Save/Restore, Constraint Solver optimization, Multicore
Advanced simulation technologies
- Native Low Power, X-Propagation, SystemC and AMS Cosimulation,
Comprehensive planning, coverage and execution management native integration
- VCS provides key turnaround time and ease-of-use benefits via native integration with Verdi® debug, VC Formal and VC VIP
Figure 1: VCS simulation solution
VCS supports all popular design and verification languages, including SystemVerilog, Verilog, VHDL, OpenVera™, SystemC™, and the Accellera® UVM™, VMM, and OVM methodologies (Figure 2). VCS’ support for Accellera UVM also includes access to the VMM/UVM interoperability kit, which enables the use of VMM with UVM and vice versa. Besides supporting digital circuit design, VCS also supports analog and mixedanalog designs through Verilog-AMS, SPICE and SPF. This comprehensive support for advanced flows and methodologies enables VCS to help users develop the highest-quality mixed language functional verification environments in the shortest amount of time.
Figure 2. Complete SystemVerilog ecosystem
Verification Continuum Platform
VCS is the center of the most comprehensive and natively-integrated functional verification ecosystem in the industry. Complementing simulation, the VCS functional verification ecosystem provides formal verification (VC Formal), emulation (ZeBu), testbench quality analysis (Certitude) and comprehensive coverage closure. The VCS ecosystem is a core element of the Synopsys Verification Continuum Platform (Figure 3).
Figure 3. Synopsys Verification Continuum Platform
VCS is the industry’s highest performance simulation solution. VCS offers both industry-leading compile time and run time performance improvement technologies.
Compile time reduction for SoC designs
VCS provides advanced tools for reducing compile turnaround time for complex SoC designs, including Precompiled IP support targeted at IP integration flows, Partition Compile to isolate portions of the testbench that are not changing during development cycles, and Dynamic Reconfiguration to compile for a target and select which model is used at runtime (Figure 4). Combined, these tools offer the most comprehensive set of solutions to maximize compile efficiency, and reduce turnaround time for SoC verification flows.
Figure 4. Dynamic reconfiguration
VCS’ Partition Compile technology allow users to achieve up to 10x faster compile time by only recompiling code that has changed, and reusing the libraries for the unchanged modules already compiled earlier.
VCS’ Precompiled IP flows enables up to 2X compile time improvement in IP integration for SoC flows. Precompiled IP flows reduce scratch compile time for hierarchical designs, enable integration of IPs with different debug and coverage capabilities, and allows automatic incremental compile of IPs and clusters.
VCS’ Dynamic Reconfiguration (Figure 4) feature enables turnaround time reduction over entire regressions by allowing users to compile once, and run different configurations/testbenches without need for recompiles. All debug and coverage features work seamlessly regardless of configuration.
Simulation runtime reduction
VCS’ high performance simulation engines are continuously improved with state-of-the-art performance and memory optimization technologies. These technologies provide best-in-class out of the box performance, and also support tuning simulator performance to a wide variety of user environments.
Save/Restore feature (Figure 5) lets the user save the state of simulation in a file for it to be restored at another time or on a different machine. Designs that have a long design initialization simulation can benefit from this feature by saving the initial state and restoring the simulation to after initialization in subsequent runs thereby reducing simulation time.
Figure 5. Save/restore benefit
VCS’ industry-leading, high-performance constraint solver technology is powered by multiple solver engines that simultaneously analyze all user specified constraints to rapidly generate high-quality random stimulus that verifies corner case behavior. The constraint solver engines will find a solution to user constraints if one exists, minimizing constraint conflicts and maximizing verification productivity. This feature is essential for directing the randomized testing strategy towards a meaningful space and speeds up bug finding.
VCS’ multicore technology offers two robust use models: design-level parallelism (DLP) and application-level parallelism (ALP) (Figure 6). DLP enables users to concurrently simulate multiple instances of a core, several partitions of a large design, or a combination of the two. ALP allows users to run testbench, assertions, coverage, and debugging concurrently on multiple cores. Multicore technology has shown up to 2x runtime speed ups on GLS designs.
Figure 6. Verdi design and testbench debug
Advanced Simulation Technologies
Beyond simulation performance, VCS provides the broadest support for advanced simulation technologies needed to accurately and completely verify today’s advanced designs.
Native Low Power
VCS’ Native Low Power (NLP) simulation technology provides VCS with comprehensive low power verification and debug capabilities. NLP integration with Verdi also enables easy LP debug with advanced LP features, and provides excellent support for LP assertions and coverage for coverage-driven verification flows. VCS’ native low power solution allows user to perform multi-voltage simulations so that they can feel the freedom to implement several techniques for power management.
Certain RTL semantics, such as using x-value to denote indeterminate state, may not model actual hardware behavior accurately. Instead of having to rely on increasingly costly gate level simulation, VCS provides a way to simulate x-propagation in multiple modes to model x-value in either more, less or equally optimistic modelling as compared to the regular gate-level simulation
Figure 7. VCS X-propagation support
SystemC simulation and Cosimulation support
VCS SystemC support is fully compliant with IEEE 1666 SystemC versions, and provides both direct simulation and cosimulation support. Direct variable access from/to SystemVerilog is supported, as are function calls across languages. VCS Profiler supports native SystemC profiling, and advanced debug is supported in Verdi CBug feature.
Table 1. VCS
VCS provides many benefits for AMS designers namely – real number modeling, native low power and advanced methodology with AMS testbench. In addition, all analog and mixed signal data can be viewed in Verdi’s advanced AMS debug environment, which is natively integrated with VCS to enable fastest analysis and finding root cause.
Planning and Coverage
A verification cycle is dominated by the time meeting coverage goals and spent in debug. VCS is natively integrated with Verdi Coverage (Figure 8) to support advanced coverage driven verification methodologies. VCS includes multiple integrated technologies – assertions, assertion checkers, interactive debug and Unified Report Generator (URG) for coverage data – to help define, measure and report coverage goals, and find coverage holes. VCS natively supports not only the complete SVA syntax from Verilog LRM, PSL and OVL, but also provides useful controls to manage the assertion output and performance of simulation. VCS’ regression execution management capabilities provides powerful configuration, regression results database, and compute farm management features.
Figure 8. Verdi Verification Planner and Coverage Analyzer windows
Native integrations between the high performance VCS simulation engine and the other advanced engines in the Synopsys Verification Continuum Platform (Figure 3) enables improvements in time-to-market by up to months.
The Verification Continuum Platform’s unified verification architecture eliminates these discontinuities with VCS Unified Compile, Verdi Unified Debug, and key native integrations such as the following:
- Verdi — Verdi Reverse Interactive Debug exemplifies the power of VCS engines and technologies natively integrated in the Verdi debug environment, and vice versa (Figure 9).
Figure 9. Verdi/VCS Reverse Interactive Debug—go back in time without setting checkpoints
- Static and Formal – VC LP and VC Formal both fully support Unified Compile with VCS and Unified Debug with Verdi
- Emulation – VCS congruent mode enables simulation to match actual hardware and facilitates emulation-simulation interoperability
- VIP – Synopsys’ VC Verification IP solution offers native integration with VCS’ planning, coverage and constraint solver technologies, and provides native Verdi-based debug and Protocol Analyzer capabilities
With VCS, not only does one get the industry leading performance and capacity in simulation, but also the fully integrated suite of technologies and tools built around the simulator to drive any verification strategy a designer wants to execute. The product roadmap for VCS technologies and verification flow in general follows the path treaded by the design leaders in the industry. In addition, VCS comes with the top-notch support so that verification schedules stay on track.