Verification Compiler  

Comprehensive, best-in-class verification in one product 

Verification Compiler™ provides next-generation technology, native integration, and complete access to all of the software capabilities and verification IP required for functional verification of advanced SoC designs. Verification Compiler provides comprehensive support for all simulation flows, including native low power, X-Prop, planning, coverage and execution management. Verification Compiler also supports industry-leading SoC debug flows, including power-aware and HW/SW debug. It also provides access to Synopsys’ next-generation static and formal technologies, with advanced low power static checking, formal verification, Clock Domain Crossing (CDC) checking and advanced lint. Verification Compiler makes all of Synopsys’ next-generation VIP titles available in simulation and debug flows (See Figure 5). Verification Compiler offers compelling integration features, providing up to 2-3X performance improvements and 3X productivity improvements. Finally, Verification Compiler provides users uniquely flexible access to simulation, static/formal and debug features to enable concurrent verification.

Verification Compiler Datasheet

Rethinking SoC Verification White paper

Key Benefits

Next-Generation Technologies
  • Advanced static and formal verification
  • Next-generation VIP
  • High performance, fully-integrated Native Low Power and X-Propagation simulation
  • Verification planning and management
  • Advanced multi-domain debug
2-3X Performance Increase with Native Integrations
  • Unified Compile across simulation, debug, static and formal
  • Complete power-aware verification with integrated native low power simulation, low power staticchecking and power-aware debug
  • Native testbench quality analyzer with Certitude™ technology
  • Natively integrated simulation-debug flow enabling 3X faster dumping and 3X smaller database sizes
3X Productivity Increase with Complete Access
  • Access to all of Synopsys’ functional verification software capabilities and verification IP libraries
  • Enables concurrent verification flows by allowing independent use of simulation, debug, formal/static technologies with one Verification Compiler license
  • Enables high-value mixed technology flows—such as interactive testbench debug—with one Verification Compiler license

Figure 1: Verification Compiler
Figure 1: Verification Compiler

Key Technologies

Next-Generation Static & Formal
  • Advanced low power static verification
  • Next-generation model- and property checking
  • Formal SoC connectivity checking
  • C to RTL transaction equivalency checking
  • RTL to RTL sequential equivalency checking
  • Advanced Clock Domain Crossing (CDC) checking
  • Based on industry-leading Verdi3™ debug environment
  • Advanced SoC debug—poweraware, HW/SW, advanced mixed signal (AMS) and interactive debug (See Figure 2)
  • Transaction-level debug and protocol analyzer
  • Advanced coverage plan management, analysis and exclusion manager
  • Open VIA apps
  • High performance and capacity simulation
  • Native Low Power
  • X-Propagation
  • All Synopsys VIP titles
  • Next-generation SystemVerilog architecture titles
  • Test suites and development kits
  • RTL, gate-level and C/C++ fault injection
  • Advanced coverage analysis, planning and execution management

Figure 2: Interactive Testbench Debug
Figure 2: Interactive Testbench Debug

Key Integrations

Simulation & Debug Integration
  • Unified compile: Consistent compile behavior, 35% lower compile overhead and 2X faster debug-mode simulation
  • Native Siloti, incremental KDB, coverage analysis with Verdi, AMS integration
Simulation & Static/Formal/Coverage Integrations
  • Unified compilation across engines for consistent support and reduced compilation overhead
  • Formal coverage convergence: Unified setup, coverage database and reporting
  • Automated on reachability, analysis and exclusion Native Certitude™: Simplified single step use model, same language set support, seamless support for all simulation technologies and optimal runtime performance
  • Automated static/dynamic CDC checking, execution manager support for static/formal and Certitude, fault propagation using multi fault simulation
Simulation & VIP Integrations
  • High-performance VIP models: Optimized constraints and code for best simulation performance; optimized debug capabilities
  • Built-in support for simulation technologies: Precompiled IP, verification plan and coverage closure
  • Built-in Execution Manager support and coverage convergence
Static/Formal & VIP & Coverage Integrations
  • Formal engine integration with Certitude

Figure 3. Next-generation static and formal verification
Figure 3. Next-generation static and formal verification

Concurrent Verification
Today's SoC verification flows require simultaneous use of various verification technologies by multiple teams across the world. Furthermore, different points of the flow require different concentrations of technologies. These types of usage and access bottlenecks greatly impact verification efficiency, cost and time-tomarket. To address these bottlenecks, each Verification Compiler license includes three independent keys: One key for all static and formal technologies, one key for simulation-related technologies (including all VIPs), and one key for all debug technologies. These three keys can be used concurrently by a single user, offering individual productivity, or they can be used independently by different individuals in the same company (See Figure 4).
This flexibility allows design teams to perform multiple verification functions simultaneously, enabling dramatic verification productivity improvements.

Figure 4: Concurrent Verification enables 3X productivity
Figure 4: Concurrent Verification enables 3X productivity

  • Supports multiple users in different stages of the verification flow
  • Provides everything needed for advanced integrated verification flows
  • Enables flexibility in deploying verification capabilities

Verification Compiler is available for general deployment in December 2014.

Figure 5: Verification Compiler's next-generation technologies for a complete verification flow
Figure 5: Verification Compiler's next-generation technologies for a complete verification flow

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