Verification Seminars 

A Comprehensive Verification Solution for Addressing Rising SoC Challenges 

Seminar Overview
The Verification Seminar is a one-day technical seminar providing an overview of Synopsys' functional verification platform and new technologies to help leading design teams manage verification complexity. Synopsys' advanced functional verification technology seminar will demonstrate high-performance simulation methodologies, advanced debug automation, native SystemVerilog Verification IP, transaction-based verification with hardware assistance, FPGA prototyping, and the latest with analog/mixed signal, low power and system-level verification solutions to help improve verification productivity.

Who Should Attend:
Verification engineers and managers

Primary Seminar Agenda
(agenda may vary in some locations)

TimeTopic
9:00 a.m.Registration / Welcome Participants
9:15 a.m. – 9:45 a.m.A Comprehensive Solution for Addressing Rising SoC Challenges
9:45 a.m. – 10:15 a.m.High Performance Simulation Technologies
10:30 a.m. – 11:15 a.m.Coding for Reuse, Coverage Closure, and Productivity (UVM Best Practices, Planning, Management and Qualification Tools)
11:15 a.m. – 12:00 p.m.Debug for Advanced SoC Verification
NOONLUNCH
1:00 p.m. – 1:45 p.m.Increasing Productivity with VIP
1:45 p.m. – 2:15 p.m.Comprehensive Low Power Verification and Signoff
2:30 p.m. – 3:00 p.m.Transaction-Based Verification with ZeBu
3:00 p.m. – 3:30 p.m.System Prototyping with HAPS
3:30 p.m. – 4:30 p.m.Analog / Mixed-Signal Co-Simulation

Verification Seminar Schedule

DateLocationRegistration
July 9, 2013Seoul, KoreaREGISTER NOW
July 10, 2013Austin, TexasREGISTER NOW



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