DAC 2012 - Verification Luncheon

On June 5, 2012, Synopsys hosted a luncheon event at DAC in San Francisco, CA. Industry leaders, such as AMD, Broadcom, Cavium, Freescale, Qualcomm and ST-Ericsson shared their views on what's driving SoC complexity and how their teams have achieved success. They also discussed the latest developments in verification.
Brian Hunter, Consulting Engineer, Cavium; Fabien Nimsgern, Director of CAD, ST-Ericsson; Hillel Miller, Verification Manager, Freescale; Karl Whiting, Verification Architect, AMD; Noumaan Shah, Principal Engineer, Broadcom; Lu Dai , Design Verification Lead, Qualcomm; John Chilton, Sr. VP of Marketing, Synopsys

DAC 2012 - Verification Luncheon Highlights

Speakers:

John Chilton, Sr. VP of Marketing Synopsys		Brian Hunter Consulting Engineer Cavium Scaling to 100Gbps

Fabien Nimsgern Director of CAD ST-Ericsson Low Power Verification of Advanced SoC's for Smartphones and Tablets		Hillel Miller Verification Manager, Freescale Verifying SOC IP with VCS and UVM

Karl Whiting Verification Architect AMD Using Verification IP as Cornerstone of Modular Verification Strategy		Noumaan Shah Principal Engineer Broadcom AXI & ACE Verification For Cortex™-A series

Lu Dai Design Verification Lead Qualcomm Verification Challenges in Billion-Transistor SoC