An SoC is really ready to ship when the complete application works, not just when hardware simulations pass regressions. In other words, the ultimate test for a chip is to see it perform its application correctly and completely. That means executing the embedded software together with the RTL. Such tests require billions of cycles of execution, and usually run at the system-level, where design size is the greatest. Simulating such applications even on advanced workstations is simply too slow. ZeBu emulation has the execution speed to simulate the full application, plus the unique co-debug environment that allows both hardware and software debugging.
With ZeBu, hardware designers have access to signal waveforms within the chip, while software developers use their standard software debuggers, typically connected through JTAG interfaces to the processors. ZeBu's unique technology, which synchronizes simultaneous hardware and software views, allows for very easy debug of low-level software, initialization vectors and device drivers.
- Virtual components that can be assembled and configured easily to build a complete virtual verification environment with all interfaces, devices and peripherals required for application execution
- Software execution and debug while keeping synchronized with the hardware (e.g. waveform dumping), so that you can see software registers or key buses respond to actual software drivers and applications
- Ability to immediately pinpoint and locate problems and malfunctions in a system simulation of billions of cycles, through hardware monitors and traces, as well as enabling all of the standard software debugger features
- Ability to analyze, benchmark and measure the performance of key components over long stress test scenarios
Product: ZeBu Transactors and Memory Models
Solution: Embedded Processor Models
Solution: Transaction-Based Verification