Super-Block Verification 


Super-blocks (also called sub-systems) in an ASIC/SoC design typically implement highly specialized functions, such as video encoding and decoding, encryption, packet classification, etc...

ZeBu allows you to verify those super-blocks more exhaustively than any other approach, so you can build full confidence in your design as early as possible, well before full-chip integration and tape-out.

Benefits of ZeBu

  • MHz performance: thanks to the very high performance (up to 12 MHz) of ZeBu, you can reach and verify corner conditions deep in the state space, run full streams of data through the super-block and analyze its performance and throughput.
  • Easy compilation flow: the ZeBu compiler will import and compile the RTL of your super-block — taking care of everything automatically.
  • Powerful testbench environment: with Zebu's unique high-performance transaction-level interface, you can write software testbenches very easily, in C++ or SystemVerilog that exercise all the scenarios of the design that you want.

Example of a super-block

Super-Block Example

This example highlights a super-block performing H.264 decoding, mapped in ZeBu and interacting with an AHB bus transactor and a display transactor.

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