|System-Level Design Roundtable from DAC 2013 Ed Sperling, part III|
The Future Of Verification. How verification is changing; validation vs. verification; the limits of divide and conquer; the impact of stacked die; questions about whether the lines are blurring between board and die; permanent employment for verification experts.
Nov 11, 2013
|Start Verification Early To Avoid Pitfalls Later|
It is well understood – at least from a theoretical point of view – that design verification should start as early as possible. The reality is that that doesn’t always happen for a variety of reasons such as enormous time to market pressure, too many new features to add, lack of foresight and discipline among other things. But progress is being made.
Oct 24, 2013
|Experts At The Table: Debug – Part II|
What are the big issues with debug? Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation.
Oct 24, 2013
|System-Level Design Roundtable from DAC 2013 Ed Sperling, part I|
The Future Of Verification. Raising the abstraction level and the effect on verification time; productivity measurements; the need to start verification earlier; concurrent issues; talk about a productivity gap resurfaces.
Oct 24, 2013
|Experts At The Table: Debug – Part I|
First of three parts: Multi-contextual debugging; IP Integration issues and who to call when you got a problem; why it’s taking more time to debug; limitations of tools; attitudes of IP development teams to customer issues.
Sep 26, 2013
|Finding A Bug In The SoC Haystack|
Finding critical bugs in the interaction of the embedded software running with the underling hardware, is like finding the proverbial needle in a haystack.
Aug 09, 2013
|Debugging Verification Constraints |
Designs now can have 50-100K lines of constraints which leads to performance issues. The constraint solver under the hood of Synopsys's verification environment has been improved and that has sped things up, sometimes by as much as 25 times but more often just a factor of 2.
Jul 23, 2013
|Software Debug gets tricky|
Traditionally, emulation has played a significant role in verifying that software against RTL code, and continues to do so. But with the advent of multicore architectures, the picture is evolving.
Jul 11, 2013
|TBV and emulation combine multi-megahertz verification performance|
Design complexity has grown with each successive generation of system-on-chip (SoC) evolution.
Jun 17, 2013
|Facing the Verification Management Challenge|
The integration of multicore CPUs, graphics coprocessors, modems, multimedia and networking facilities in the SoCs that power today’s sophisticated smartphones, tablets, computing and networking devices is creating a new verification challenge.
May 23, 2013
|Power Trumps performance in today’s SoC designs|
Designing a complex embedded system-on-chip (SoC) today is a multi-pronged challenge.
May 02, 2013
|Dealing with the Data Glut|
Tools like emulation and simulation are an absolute necessity to design and verify today’s complex SoCs, but what happens when you want to do power analysis and the file sizes are too massive for the emulator to handle?
Apr 11, 2013
|Generating AMD microcode stimuli using VCS constraint solver|
In this article, we explore using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys VCS constraint solver. We present and analyze the method and discuss its effectiveness in today’s verification environment.
Jul 14, 2010
|Verification alive and well at SoC virtual conference|
During the first EE Times System-on-Chip Virtual Conference, a panel on verification challenges raised pressing issues in the areas of cost, startups, impact of electronic sytem level (ESL) design, virtual plattforms and functional verification as a methodology.
Sep 17, 2009
|SystemVerilog and VMM Overcome WiMAX Verification Challenges|
SystemVerilog and VMM-based environment help achieve first pass silicon success by performing smarter verification quicker.
Aug 05, 2009
|Parallel Simulation Boosts Verification Productivity|
As compute infrastructures transition to multicore, multi-threaded architectures, verification solutions must evolve to optimize the performance on new hardware.
Apr 17, 2009
|Synopsys parallelizes and unifies simulation and verification tasks of VLSI design|
EDA industry is reeling under pressure to innovate. Semiconductor vendors are in no-mood to pay hefty charges for some small improvements. EDA vendors are left with limited options either to provide cost optimized solution or powerful high performance chip design software of 2x performance for same cost.
Apr 14, 2009
|Synopsys Introduces Discovery 2009|
Platform Encompasses New Multicore Simulation Performance, Native Design Checks, Comprehensive Low Power Verification Capabilities, and CustomSim Unified Circuit Simulation Solution.
Apr 06, 2009
|Synopsys Moves Tools to Multicore Hosts|
Synopsys has increased verification speed and brought digital, analogue and memory simulation under the same roof as it moves its tools to multi-core hosts.
Apr 06, 2009
|Verification Evolves Into Lean, Mean Bug-Stomping Machines|
We all want our next-generation Pocket Rocket to do new stuff (and do the old stuff better), as well as get smaller, run longer, and cost less. We also don't necessarily want to wait for the holiday season for it to hit the shelves. We gadget freaks are often rather impatient in that regard.
Sep 11, 2008
|Using VMM, DPI, and TCL to Leverage Verification and Enable Early Testing, Emulation, and Validation|
Let’s face it. Some designers refuse to learn a new language. Or, the prospect of learning object-oriented programming makes some people break out in hives.
Aug 26, 2008
|TCL Drives C Drives SystemVerilog|
Judging by advertising and datasheets and other promotional materials, verification is pretty much a simple, clear-cut, well-solved problem. Actually, that’s not quite true.
Aug 26, 2008
|SystemVerilog-The Complete Solution|
The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips.
Jul 06, 2006
|SystemVerilog reference verification methodology-ESL|
Over the past 20 years, the level of abstraction for chip design has risen from transistors through gates and RTL to the electronic system level (ESL).
Jun 12, 2006