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Blogs
All Synopsys Blogs
A View from the Top: A System-Level Blog
Shift towards adoption of virtual platforms and ESL technologies.
Achim Nohl
On Verification: Software-to-Silicon
Exploring software-to-silicon verification.
Tom Borgstrom
Standards Blog: The Standards Game
Observation, information and experiences with technical standards.
Karen Bartleson
Verification Methodology Blog : Verification Martial Arts
Technical information and tutorials focusing on functional verification.
Janick Bergeron
VIP Café
A place where experts chat about verification IP
Amit Sharma, Aron Pratt, Hari Balisetty, Parag Goel, Ray Varghese, Tushar Mattu
All Synopsys Blogs
DAC Custom Design Lunch
Addressing Custom Design Challenges with Laker
DAC Verification Luncheon
SoC Leaders Verify with Synopsys
DAC AMS Lunch
Advance Your Mixed-Signal Verification Techniques to the Next Level
DISCOVERY-AMS WEBINAR
Mixed-Signal Verification — An ST-Ericsson Case Study
DVCon 2013 Videolog
Industry Leaders Verify with Synopsys
News
Micronas Standardizes on Synopsys’ Design and Verification Solutions for....
Latest Advances in FineSim Deliver Up to 2X Performance and Capacity Improvements
Imagination Technologies Selects Synopsys as Advanced Verification Technology Partner
Freescale Boosts Verification Productivity with Synopsys Verification IP
Synopsys Extends Support for ARM AMBA Protocol Verification with New....
BiTMICRO Selects Synopsys for Chip Design Automation
Synopsys Collaborates with Sigrity to Accelerate Signal Integrity Analysis
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All Synopsys News
Articles
The New Economics of Verification
Generating AMD microcode stimuli using VCS constraint solver
Attacking Constraint Complexity: E Soft and SystemVerilog Default Constraints
Attacking Constraint Complexity: Verification IP Reuse
Verification alive and well at SoC virtual conference
SystemVerilog and VMM Overcome WiMAX Verification Challenges
Parallel Simulation Boosts Verification Productivity
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Blogs
A View from the Top: A System-Level Blog
On Verification: Software-to-Silicon
Standards Blog: The Standards Game
Verification Methodology Blog : Verification Martial Arts
VIP Café
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Success Stories
Etron Achieves First-Silicon Success of USB3.0 SoC Using Synopsys Proven Solutions
Emulex Enhances Design Productivity With Synopsys’ Advanced Verification Solutions
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White Papers
MOS Device Aging Analysis with HSPICE and CustomSim
Custom and Mixed-Signal Design Solution
Understand and Avoid Electromigration (EM) & IR-drop in Custom IP Blocks
Using Digital Verification Techniques on Mixed-signal SoCs with CustomSim and VCS
Accelerating Analog Simulation with HSPICE Precision Parallel Technology
High-performance, Parallel Simulation with VCS Multicore Technology
Are We There Yet
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Webinars
VCS Constraint Debug
Increasing the Productivity of Mixed-Signal Verification and Debug Using CustomExplorer Ultra
Verilog-to-Verilog Equivalence Checking Using ESP
Transaction Debug with Verdi3
Discovery-AMS for Mixed-Signal Verification
Verifying Advanced Low Power Designs
Accelerate PCIe Integration Testing with Next-Generation Discovery VIP
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Videos
SNUG 2013 Verification Lunch Panel: Industry Leaders Verify with Synopsys
ProtoLink Video
DVCon 2013 Verification Lunch Panel: Industry Leaders Verify with Synopsys
Verification Futures Conference 2012 Presentation: Will Everything Start to Look Like a SoC?
DAC 2012 Verification Lunch Panel: SoC Leaders Verify with Synopsys
Protocol Analyzer Video Demonstration
DVCon 2012 Verification Lunch Panel: Industry Leaders Verify with Synopsys
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Training Courses
OpenVera Reference Verification Methodology (RVM/VMM)
SystemVerilog Testbench
SystemVerilog Verification Using VMM Methodology
Vera I
NanoSim
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Product Guide
VMM CENTRAL
Discovery Platform
Low Power Solution
SNUG
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