|20X Faster - Accelerated Power Analysis with Synopsys Verdi Technologies (Part 4 of 4)|
In this webinar, discover how Verdi technologies – Siloti Correlation and Siloti What-If Replay Simulation enable early and accurate power estimation by using RTL simulation results to generate gate-level simulation data, without the need for gate-level environment bring up. This new Verdi Power Analysis Acceleration flow runs up to 20X faster and offers accuracy within 5%, compared to the traditional flow. Additionally, parallel run technology further enhances the speedup to up to 60X.
Vaishnav Gorur, Product Marketing Manager, Verification Group; Chun Chan, R&D Director, Verification Group, Synopsys, Inc.
Oct 18, 2016
|Comprehensive Power Optimization Solution for Faster RTL Signoff (Part 3 of 4)|
In this webinar, we will discuss how SpyGlass Power delivers an integrated early power analysis and exploration solution that includes: estimation, profiling, reduction and exploration.
Kiran Vittal, Product Marketing Director, Verification Group; Ken Mason, Corporate Applications Engineer, Verification Group, Synopsys, Inc.
Sep 21, 2016
|Formal Debug: Achieving Faster Root Cause Analysis of Formal Results with VC Formal and Verdi|
Based on years of hands-on experience and the latest debug features of VC Formal with Verdi, this webinar will give a practical guide to various debug techniques for analyzing formal verification results that will enable verification teams to get the most out of integrating formal verification into their flow. Using debug challenges such as assertion failures and sequential equivalence mismatches this webinar will guide users on the fastest way to a resolution. It will also show Navigator - a powerful new debug solution in Verdi – that allows quick waveform based what-if analysis on design functionality without any need for a testbench environment or assertion expertise.
Prapanna Tiwari, Senior Manager, Formal Verification Product Marketing, Synopsys; Sean Safarpour, Ph.D.
Formal Verification CAE Manager, Synopsys
Sep 14, 2016
|Thinking ‘Outside the Waveform’ – Boosting Design Debug Productivity with Verdi|
In this Synopsys webinar, we will show how you can cut your debug time in half with innovative Verdi design debug techniques. Specifically, you will learn how Verdi enables you to quickly explore, visualize and debug complex, and even unfamiliar designs; how you can quickly root-cause and debug simulation failures with Verdi debug techniques such as temporal flow view, automated X-tracing, assertion analyzer etc; and how Verdi’s unified debug platform extends the intuitive and familiar Verdi debug use-model to natively integrated Synopsys static and formal verification solutions.
Vaishnav Gorur, Product Marketing Manager, Verification Group, Synopsys; Archie Feng, Corporate Applications Engineer, Verification Group, Synopsys
Sep 13, 2016
|Catch low-power simulation bugs earlier and faster with Verdi Power-Aware Debug (Part 2 of 4)|
In this webinar, we will demonstrate how Verdi Power-Aware Debug greatly simplifies low-power debug and identifies potential design-killing bugs earlier and faster, with a unified and comprehensive view of the design and its power intent. Specifically, you will learn how visualization of the power architecture can help identify power strategy and connectivity issues upfront; how to use annotated power intent on source code, schematics and waveforms to rapidly root-cause power-related errors back to UPF/RTL; how to debug unexpected design behavior such as Xs caused by incorrect power-up/down sequences etc.
Vaishnav Gorur, Product Marketing Manager, Verification Group; Archie Feng, Corporate Applications Engineer, Verification Group, Synopsys, Inc.
Aug 31, 2016
|Learn About SpyGlass CDC/RDC New Features (Japanese)|
Learn about the latest new features for SpyGlass CDC/RDC including "Smart Netlist Verification" and "RDC (Reset Domain Crossing)".
Nobutaka Ogiya, Senior Application Engineer, NSGK, Synopsys, Inc.
Aug 30, 2016
|Addressing Low Power Verification Challenges with Advanced Static Checking and Native Low Power Simulation (Part 1 of 4)|
In this session, we will discuss UPF based static and dynamic verification techniques to address these challenges. We will also discuss the problems addressed by Synopsys’ VC LP and VCS NLP tools, to streamline the entire verification process.
Kiran Vittal, Product Marketing Director, Verification Group; Amol Herlekar, Sr. Staff Engineer, Verification Group,
Ankush Bagotra, Staff Engineer, Verification Group, Synopsys, Inc.
Aug 10, 2016
|Time-travel in a SystemVerilog/UVM world – Interactive Testbench Debug Unleashed!|
In this Synopsys webinar, we will show how interactive debug is ushering in a new era in testbench debug. Specifically, you will learn: how interactive and reverse interactive debug capabilities allow you to quickly root-cause and debug simulation failures; how what-if analysis improves TB debug efficiency by combining diagnosis and cure into a single step; how to navigate and effectively debug a UVM-based testbench
Vaishnav Gorur, Product Marketing Manager, Verification Group; and Mansour Amirfathi Sr. CAE Manager, Verification Group, Synopsys, Inc.
Jul 20, 2016
|Enabling ISO 26262 Compliance with Synopsys’ Automotive Safety Verification Solution|
This webinar will provide an overview of the concepts, requirements, and approaches for automotive IC designers and verification teams to understand what’s needed for ISO 26262 compliance for safety-critical SoCs and IP blocks.
Capsule Module: Enabling ISO 26262 Compliance with Synopsys’ Automotive Safety Verification Solution
Brian Davenport, Staff Engineer, Synopsys’ Verification Group; David Hsu, Director of Product Marketing, Synopsys’ Verification Group
Jun 16, 2016
|Double the Value - Accelerated SoC Verification AND Earlier Software Bring-up with Verdi HW SW Debug|
In this webinar, we will show how simultaneous, synchronized views of design behavior at the software and hardware levels helps engineers at both levels debug efficiently and effectively. We’ll demonstrate how the Synopsys Verdi HW SW Debug solution seamlessly combines the industry-leading Verdi hardware debug with Eclipse-based software debug to provide a simple, yet powerful unified debug environment. Further, we will show how the solution is adapted easily to different processor core families including custom cores, as well as how it scales to debug multiple cores on a single SoC. Overall, these techniques will enable better SoC verification, accelerate software bring up and help achieve faster time-to-market.
Vaishnav Gorur, Product Marketing Manager, Synopsys, Inc. Alex Wakefield, Engineer, Synopsys, Inc.
Jun 15, 2016
|SpyGlass New Feature Update (Japanese)|
Learn about the latest key feature updates for the SpyGlass version 5.5.0 and 5.6.0 family of products including SpyGlass Lint, SpyGlass CDC, SpyGlass Constraints, SpyGlass Power, and SpyGlass DFT.
Kenichi Komiya, Verification CAE, Synopsys
Jun 01, 2016
|SpyGlass RDC: Solving Design Respins due to Reset Domain Crossings |
In this webinar, we will discuss how SpyGlass RDC delivers a unique solution to address RDC issues early at RTL, saving valuable time and costly design re-spins. SpyGlass RDC leverages the industry leading SpyGlass Platform and GuideWare methodology for an easy to use and comprehensive flow for RTL signoff.
Sean O’Donohue, Senior Corporate Application Engineer (CAE), Verification Group; Deep Shah, Senior Corporate Application Engineer (CAE), Verification Group; and Kiran Vittal, Director Product Marketing, Verification Group, Synopsys
May 24, 2016
|Making Coverage Closure SMARTer with Verdi – A Primer on Verification Planning and Coverage Modeling|
In Part I of a multi-part webinar series on Verification Planning and Coverage, we will focus on how verification planning using Verdi Coverage can help make your coverage closure goals SMART. We’ll start with a demonstration of how to create an executable verification plan from design specifications and how to structure it based on specific features, functions and design modes that need to be verified. We will then discuss the formulation of a meaningful coverage model that takes into account structural and functional coverage, as well as the different sources of coverage information. Finally, we’ll show how the verification plan acts as a centerpiece and ties together the verification data with the spec, helping provide actionable metrics to drive verification closure.
Vaishnav Gorur, Product Marketing Manager, Verification Group & Bart Thielges
CAE, Coverage and Planning, Verification Group, Synopsys
May 18, 2016
|One USB to Rule All: Streamlining with USB Type-C Verification|
In this webinar, we will discuss USB verification challenges and how the Synopsys USB Type-C verification subsystem is addressing these challenges.
Karim Aoua Corporate Applications Engineer, Synopsys & Zongyao Wen, Senior R&D Manager, Verification IP, Synopsys
May 12, 2016
|Xilinx and Synopsys Present: Meeting Test Goals Faster with SpyGlass DFT ADV|
Early detection of testability issues can prevent major bottlenecks downstream and avoid time-consuming design iterations. In this webinar, Synopsys presents new techniques and capabilities available in SpyGlass DFT ADV such as high-impact test points to boost coverage, reduce the number of patterns, and minimize test costs. Our guest speaker from Xilinx discusses test challenges associated with large SoC designs such as the Xilinx Zynq® UltraScale™ chip family, and illustrates how SpyGlass DFT ADV addresses testability issues early in the design flow, saving weeks of complex DFT-related ECOs.
Amit Majumdar, Principal Engineer, Xilinx; Anthony Joseph, Applications Engineer, Synopsys; Dmitry Melnik, Marketing Manager, Synopsys
Apr 28, 2016
|Increasing Verification Closure Effectiveness with Formal Verification|
Learn about Synopsys VC Formal advanced techniques and formal coverage metrics that provide better convergence and simulation-like visibility, to achieve formal verification signoff.
Prapanna Tiwari, Formal Verification Product Marketing, Synopsys; Sean Safarpour, Ph.D., Formal Verification CAE Manager, Synopsys
Apr 20, 2016
|Bridging the Gap in Mixed-Signal Debug: Introducing Synopsys' NEW Verdi Advanced AMS Debug Solution|
In this webinar, we will demonstrate how Synopsys' new Verdi Advanced AMS debug solution, based on the market-leading Verdi SoC debug platform, delivers groundbreaking co-simulation debug for both analog and digital engineers, as well as system integrators.
Archie Feng, Corporate Applications Engineer, Verification Group, Synopsys; Vaishnav Gorur, Product Marketing Manager, Verification Group, Synopsys
Mar 15, 2016
|What’s Next in Storage: NVMe Verification IP|
In this webinar, we will discuss the latest technology in storage protocols, NVMe, a rapidly evolving high performance storage standard developed to reduce latency and support parallelism.
Eric Peterson, Senior R&D Engineer, Synopsys; Paul Graykowski, Senior Corporate Application Engineer (CAE) for Verification Group, Synopsys
Feb 23, 2016
|Improving Analog Verification Productivity Using Synopsys Simulation and Analysis Environment (SAE)|
Learn about the comprehensive GUI-based transistor-level simulation and analysis environment that is deeply integrated with CustomSim, FineSim, and HSPICE circuit simulators.
Deepa Kannan, SAE Technical Marketing Manager, Synopsys
Feb 17, 2016
|Catching the Uncatchable Bugs with SpyGlass CDC: Comprehensive, Practical, and Powerful Analysis|
In this webinar, we will discuss how the SpyGlass CDC solution enables comprehensive clock and reset domain crossing (CDC/RDC) verification for more than a billion gates, helping designers to avoid costly chip killer bugs, re-spins and achieve signoff quality verification.
Kiran Vittal, Director Product Marketing, Verification Group, Synopsys; Sean O’Donohue; Senior Corporate Application Engineer (CAE), Verification Group, Synopsys
Jan 26, 2016
|Raising Design and Verification Productivity with SpyGlass Lint Advanced: The Next Generation of Lint|
In this webinar, we will discuss how the newly introduced SpyGlass Lint Advanced solution identifies RTL issues at their source, pinpoints structural, coding and consistency problems in the RTL descriptions, and helps designers resolve issues quickly before design implementation.
Arbind Kumar Rohilla, Verification Group, Synopsys
Dec 08, 2015
|A Holistic Approach to Verification: Synopsys VIP for ARM AMBA Cache Coherent Interconnects|
In this webinar, we will discuss how to take advantage of the system-level capabilities of Synopsys Verification IP for ARM® AMBA® protocols to verify cache-coherent interconnects. Synopsys VIP includes system-level interconnect test suites and system-level coverage to accelerate verification closure.
Satyapriya Acharya, Engineering Manager, Verification Group, Synopsys
Nov 18, 2015
|Learn How to Accelerate Verification Closure with PCIe Gen4 VIP|
This webinar shows how to leverage protocol, methodology, verification and productivity features of Synopsys VC VIP and UVM source code test suites for accelerated verification closure of PCIe Gen4 based designs.
Paul Graykowski, Senior Manager, PCIe VIP, Synopsys
Aug 19, 2015
|TSMC/Synopsys CustomSim Collaboration for 16nm FinFET Design Success|
Join TSMC and Synopsys as we discuss N16FF+/early N10 certification collaboration activities and how CustomSim 2015.06 addresses the design needs of FinFET technology nodes.
Jacob Ou, Technical Manager, TSMC; Tom Hsieh, Corporate Application Engineering Manager, Synopsys
Aug 12, 2015
|Addressing Verification Challenges of Evolving Ethernet Speeds from 25/40/50/100G and Beyond|
We will outline in detail the verification challenges of current and future Ethernet speeds and explain how Accellera UVM Methodology, IEEE 1800-2012 System Verilog Functional Coverage, and SystemVerilog Ethernet Verification IP empowers design and verification teams with methodology, techniques and tools they need to achieve success.
Shenoy Mathew, Senior Corporate Applications Engineer, Verification Group, Synopsys
May 20, 2015
|Picking up the pieces: self-contained verification platforms for the modular smartphone era|
In the framework of Mobile platforms, learn how source code testsuites provided with Verification IP enable verification engineers to quickly generate diverse permutations of random/constrained random transactions that stress test the systems and subsystems, contributing to "Shift Left" of the verification time and ensure bug free designs.
Nitin Agrawal, CAE Manager, Verification Group, Synopsys
Apr 07, 2015
|HSPICE Tips & Tricks Webisode Series|
Learn from Synopsys applications engineers how to get the most out of HSPICE analysis. Topics will include how to most effectively use S-element, eye diagrams, IBIS-AMI, RUNLVL, and more. New mini webinars will premiere monthly.
Ted Mido, Principal Engineer, HSPICE R&D, Synopsys
Nov 03, 2014
|The 10 Things to Know About Memory Verification: Synopsys Memory VIP|
Learn how feature-rich, native SystemVerilog memory VIP rapidly verifies the memory interfaces on complex designs, focusing on 10 key areas where productivity is improved.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Nasib Naser, PhD, Senior Staff Corporate Applications Engineer, Synopsys
Oct 23, 2014