Webinars 

FineSim Technology for Analog and Full-Chip Simulation - A Micron Case Study
Learn about FineSim’s transient analysis advantage and the rich feature set that that combines SPICE and FastSPICE simulation technology in one single environment used for memory design at Micron.
Raed Sabbah, Sr. Design Engineer, Embedded Solutions Group, Micron Technology
May 08, 2014
 
Hybrid Emulation with ZeBu
Virtual prototypes and emulation systems not only add value in their standalone usage on large SoC projects, but can provide synergistic value when used together for performance validation, early software development and hardware verification. In this webinar we will describe the components of hybrid emulation and the principal applications of architecture analysis, software driven verification, and development of applications software.
Gwyneth Sauceda, Member Technical Staff, Verification Group, Synopsys
May 07, 2014
 
Integrate your Debug Platform Seamlessly with Verdi Interoperable Apps (VIA)
Learn how Verdi, the industry’s de facto debug platform, offers a fully extensible platform for SoC teams and third-party EDA vendors to develop innovative debug capabilities to address this growing challenge in the industry. The Verdi Interoperability Apps (VIA) opens the programming interface of Verdi letting developers to integrate flow on Verdi Debug Platform.
Rich Chang, Product Marketing Manager, Synopsys; Archie Feng, CAE, Synopsys
Dec 18, 2013
 
Eliminate DDR3 Timing Errors with HSPICE and Zuken Constraint-based PCB Routing
Learn how to analyze signal integrity of critical traces in your PC board layout, incorporate board parasitics and define design constraints to eliminate timing violations.
Griff Derryberry, Applications Engineer, Zuken USA; Hany Elhak, Product Marketing Manager, Synopsys
Dec 11, 2013
 
Siloti Correlation Technology Improves Cross-Abstraction Levels and Debug Productivity
Learn how Siloti™ correlation technology automatically does the mapping for designers between RTL and gate-level designs and simulation waveforms. Usage flows and examples of applications will be provided.
Thomas Li, Product Marketing Director, Debug, Verification Group, Synopsys; Chun Chan, R&D Manager, Debug, Verification Group, Synopsys
Dec 04, 2013
 
Effective Verification of ARM AMBA 5 CHI Interconnect-Based SoCs Using Next-Generation VIP
This webinar will show how Synopsys' next-generation Discovery™ Verification IP enables the rapid creation of a multi-protocol verification environment for an AMBA® 5 CHI interconnect, including CHI, ACE-Lite™ and other AMBA interfaces. The webinar will cover stimulus, system-wide coherency and data integrity checking, performance checking, protocol-aware debug and coverage.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Tushar Mattu Corporate Application Engineer (CAE) for Verification Group, Synopsys
Nov 20, 2013
 
VCS Xprop: Catch X-Related Issues at RTL to Reduce Time-Consuming Gate-Level Simulations
In this webinar you'll learn about a new technology in VCS, called Xprop, which eliminates 'x' optimism at RTL to enable correlation with hardware design behavior. Xprop can be used to reduce and potentially eliminate gate-level simulations for 'x' validation. This webinar will also show how VCS® Xprop eliminates 'x' optimism in advanced simulation flows (such as VCS-NLP) and demonstrate how to debug 'x'-related issues identified by VCS-NLP and Xprop using Verdi™ Power-Aware Debug.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys
Nov 05, 2013
 
Transaction-based Verification and HW/SW Co-verification with the Synopsys ZeBu® Emulator
This webinar provides an overview of the use models and benefits of advanced emulation technology, with an in-depth focus on Synopsys' ZeBu® Server product family. Different verification strategies using HW-assisted tools and their evolution from basic in-circuit emulation (ICE) through to today's most advanced emulation mode - transaction-based verification (TBV), are discussed. Transaction-based verification is explained in detail using several actual deployment examples to demonstrate its benefits.
Miguel Koch, Product Solution Sales Manager, Synopsys
Oct 08, 2013
 
How VCS Improves Coverage Driven Verification Efficiency with Integrated Planning and Management
VCS provides a scalable and integrated planning, management and analysis solution for metric-driven verification. In this webinar, you'll learn how to track coverage and test data in order to correlate results with project goals and resources, so teams know where they are in the verification process and how they have allocated resources. These features are available in VCS 2013.06.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; Bart Thielges, R&D, Verification Group, Synopsys
Sep 17, 2013
 
Transaction-Based Verification with Emulation
This webinar focuses on the use model and the benefits of transaction-based verification (TBV) with the ZeBu® emulation system including the trade-offs to consider in order to optimize TBV for performance, and achieve full visibility debug. This webinar includes an overview of TBV and its unique benefits. Details on transactor development and integration, including how to architect the split between a testbench and ZeBu emulation systems, is also discussed. This Webinar is intended for design and verification engineers and managers.
Lance Tamura , CAE manager, Verification Group, Synopsys; Lawrence Vivolo, Director of Solutions Marketing, Synopsys
Aug 28, 2013
 
Micron Case Study: Electrical Modeling of 3D-IC Through-Silicon Vias Using HSPICE
Learn how to effectively model the impact of TSVs on signal and power delivery, especially for high-speed applications.
Fuad Badrieh, Ph.D., Principal Engineer, Micron Technology; Hany Elhak, Product Marketing Manager, Synopsys
Jul 10, 2013
 
Improve Stimulus Quality and Verification Completeness with VCS Constraint Debug
In this webinar, you will learn about new constraint debug features available in VCS 2013.06. In the batch mode, we will show you how to debug solver solutions as well as improve solver performance. In the interactive mode, we will show you how to stop the simulation on randomize calls, explore the solution and relation spaces in the randomize call, examine the solution distribution of random variables, and modify constraints, re-compiling the design interactively for effective what-if analysis.
Rebecca Lipon, Senior Product Marketing Manager, Synopsys; Jason Chen, CAE, Synopsys; Dhiraj Goswami, Scientist, R&D, Synopsys
Jun 25, 2013
 
Verilog-to-Verilog Equivalence Checking Using ESP
This Webinar gives a quick introduction to ESP-CV and how recent features are used to verify various Verilog-to-Verilog scenarios. Coverage analysis of the results is also discussed.
Philip Schmidt, R&D Manager, Synopsys; Dave Hedges, Corporate Applications Engineer, Synopsys
May 29, 2013
 
Transaction Debug with Verdi3
In this webinar, you'll learn how to maximize your productivity by using Verdi's Transaction Debugging technology to dump, visualize and trace transactions. You'll learn how the tool's vertical correlation allows you to take the debug to the signal level waveform while retaining all of the necessary debugging details.
Rich Chang, Product Marketing Manager for Debug, Synopsys
May 22, 2013
 
Discovery-AMS for Mixed-Signal Verification - An ST-Ericsson Case Study
ST-Ericsson shares details on how they leveraged new Discovery-AMS multi-core technology to improve their overall verification flow.
Francois Ravatin, AMS Verification Engineer, ST-Ericsson; Helene Thibieroz, Sr. Product Marketing Manager, Synopsys
May 21, 2013
 
Verifying Advanced Low Power Designs: Find Design-Killing LP Bugs Early and Easily
Learn how VCS with MVSIM Native Low Power provide the accuracy and comprehensive LP support needed at RTL, and enable LP bugs to be found and fixed early and easily in the design cycle.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Aditya Kher, Senior Corporate Application Engineer (CAE), Low Power Verification, Synopsys; Harsh Chilwal, Senior R&D Engineer, Synopsys
Apr 04, 2013
 
Accelerate PCIe Integration Testing with Next-Generation Discovery VIP
Learn an optimal strategy for integration testing using UVM in conjunction with next-generation features of PCIe VIP for more efficient test development, error injection and debug.
Neill Mullinger, Product Marketing Manager, Synopsys; Paul Graykowski, Corporate Application Engineer (CAE), Synopsys
Mar 20, 2013
 
Functional Signoff: Measuring and Improving Verification Quality to Ensure Bug-Free Designs
In this webinar you will learn how Certitude Functional Qualification can be added to traditional coverage techniques, to provide unique insight into the quality of RTL simulation and formal verification environments. Certitude uses a proprietary mutation-based process to insert “artificial bugs” or faults into the design and measure the ability of your existing verification environment to detect these faults. The results of this process provide an objective measure of overall verification quality – the ability of the environment to activate, propagate and detect potential bugs – and identify specific holes and weaknesses like incomplete test scenarios, missing checkers and assertions, or infrastructure problems that can allow RTL bugs to slip through the process undetected. Fixing these weaknesses makes your verification environment stronger and reduces the risk of signing off or taping out with functional bugs.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; George Bakewell, CAE Director, Verification Group, Synopsys
Jan 10, 2013
 
Using Advanced Verification IP Capabilities to Accelerate Ethernet Verification
This webinar will be based around a typical Ethernet switch design including a processor, switch fabric and Ethernet MACs. Learn how SystemVerilog, UVM and VIP are utilized to verify the Ethernet digital core and then integration of the core into the system. We also cover advanced VIP features, including test suite and debug, to accelerate productivity.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Jaspreet Singh Gambhir, R&D Manager for Verification IP, Synopsys
Dec 11, 2012
 
Static Verification of Advanced Low Power Designs
Learn about advanced low power techniques and the static checking capabilities designers need to verify the consistency and correctness of low power intent and implementation through the flow.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Vinay Srinivas, R&D Group Director, Low Power Verification, Synopsys; Prapanna Tiwari , CAE Manager, Low Power Verification, Synopsys
Oct 30, 2012
 
Open Your Eye with HSPICE Fast and Accurate Eye Diagram Analysis
Learn how HSPICE can help you quickly model high-frequency channel components, run fast transient with long cable S-parameter models, and accurately analyze eye measurement.
Ted Mido, Sr. Staff R&D Enigeer, Synopsys
Oct 17, 2012
 
Deploying UVM Effectively: How to Simplify Testbench Debug and Improve Turn-around-time with VCS
Learn how to utilize VCS and DVE to most effectively deploy, debug and optimize UVM testbenches.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; Adiel Khan, Corporate Applications Engineer (CAE), Verification Group, Synopsys
Oct 02, 2012
 
Verification of MIPI Protocols on a Mobile Platform SoC
This webinar is based around a MIPI-based mobile platform that consists of an application processor, baseband IC and RF IC with interfaces to the peripheral devices like camera, and display. The Webinar shows how SystemVerilog, UVM and verification IP (VIP) are utilized to verify the SoC that implements that platform. It will specifically focus on how to validate the data flow for typical scenarios involving the camera (CSI) and display (DSI) interfaces.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Narasimhababu GVL, Senior R&D Manager for Verification IP, Synopsys
Aug 07, 2012
 
High-Productivity Analog Verification and Debug with CustomSim and CustomExplorer Ultra
See how Synopsys' advanced analog verification solution can dramatically increase your verification productivity with CustomExplorer Ultra, along with CustomSim and CustomSim-VCS.
Duncan McDonald, Product Marketing Manager, Synopsys
Jul 11, 2012
 
Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ VIP
Overview of challenges of verifying a coherent design. Shows how the features and architecture of Synopsys’ new Discovery VIP helps overcome these challenges to simplify verification of ACE design.
Abhijeet Khopkar, R&D Manager, Synopsys; Neill Mullinger, Group Marketing Manager, Synopsys
May 08, 2012
 
Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks
Learn how process technology & changing design styles increase the impact of EM & IR-drop effects on the performance/reliability of AMS, memory & custom digital IP blocks at 28nm and below.
Bradley Geden, Solution Architect, Synopsys
Oct 26, 2011
 


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