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IC Compiler 2: Hierarchical Design Planning

Overview
The workshop teaches floorplan preparation for large and complex integrated circuits. You will learn to partition a design into hierarchical sub-blocks for implementation in IC Compiler. All the floorplan, constraint, and timing information required for implementation is created.

We begin with an initialized floorplan (learned in the IC Compiler 1 workshop). Next, standard cell and macro placement, using plan groups, guide the development of a physical hierarchy. Manipulation of the physical hierarchy is discussed in detail.

We then demonstrate a number of methods for improving the quality of the floorplan including: power network synthesis, in-place optimization, and budgeting. Finally, we create soft macro blocks suitable for place and route processing.

Hands-on labs for all course units use a hierarchical design allowing exploration of all aspects of virtual flat floorplanning.

Objectives
At the end of this workshop the student should be able to:
  • Describe the IC Compiler Design Planning Virtual Flat Placement flow
  • Manipulate the hierarchy and create plan groups using the Hierarchy Browser
  • Perform Power Planning using IC Compiler's Power Network analysis and synthesis capabilities
  • Describe the IC Compiler Design Planning Virtual Flat Placement flow
  • Manipulate the hierarchy and create plan groups using the Hierarchy Browser
  • Perform power planning using IC Compiler's power network analysis and synthesis capabilities
  • Execute virtual flat placement and refine the plan groups
  • Perform in-place optimization
  • Perform plan-group-aware routing (PGAR) pin assignment on all blocks
  • Perform design budgeting and generate block-level SDC files
  • Generate ILM models for chip-level timing analysis and budgeting
  • Define and develop effective time budgeting for place & route in IC Compiler

Audience Profile
Design or layout engineers with little to no experience with hierarchical floorplanning using IC Compiler Design Planning.

Prerequisites
To benefit the most from the material presented in this workshop, you should:

Have taken IC Compiler 1 workshop.

OR

Possess equivalent knowledge with IC Compiler:

  • Script writing using Tcl
  • Reading and linking a design
  • Using IC Compiler's graphical user interface (GUI)
  • Generating and interpreting timing reports using report_timing and report_constraint commands
Course Outline
Day 1
  • Introduction & Overview
  • Partition Top Level into Plan Groups
  • Create Block Macros and Integrate Top

Synopsys Tools Used
  • IC Compiler 2012.06