Revolutionizing Chip Design with AI-Enabled EDA Tools

AI in the EDA Workflow Tackles Iterative and Manual Tasks

In a global economy currently shaped by uncertainties, the semiconductor industry has grown even more competitive. These factors have increased the need for even better results for semiconductor power, performance, and area (PPA). Those who can optimize these metrics faster and at lower cost stand a better chance of rising to the top. As companies adjust to today’s economic realities, there are underlying staffing pressures, with projections of scarcities in semiconductor engineering talent that could hamper progression in the industry. According to the Semiconductor Industry Association, the U.S. semiconductor design industry could face a 23,000 shortfall of semiconductor engineers by 2030.

An AI-driven EDA design suite offers a way forward, complementing and enhancing the work of engineering teams. According to Deloitte Global, the world’s top semiconductor companies will spend US$300 million on internal and third-party AI tools to design chips this year, a spend that’s expected to grow 20% each year over the next four years. The analyst firm notes in an article, “AI design tools are enabling chipmakers to push the boundaries of Moore’s law, save time and money, alleviate the talent shortage, and even drag older chip designs into the modern era. At the same time, these tools can increase supply chain security and help mitigate the next chip shortage.”

In every design, there are time-consuming tasks that are iterative and somewhat redundant, yet necessary for the quality of the chip. AI technologies can take on (and enhance results of) repetitive tasks such as design space exploration, verification coverage, and test pattern generation. This frees up a substantial amount of time for engineering teams, allowing these experts to focus on value-added tasks such as differentiating their products and quickly creating new features or derivative designs. It also allows teams to meet aggressive time-to-market targets and to accommodate more projects with their existing resources. Engineers who are new and seasoned veterans alike can benefit from AI, as the technology provides faster ramp up time for the new engineer and enables the veteran to achieve better quality of results, faster. For example, on a given project, Synopsys.ai can be tasked with handling repetitive work and acting on iterative tool results while engineers oversee chip quality, together generating better, faster results than what would be possible by humans alone.

The approach creates an opportunity for the technology to continuously build on the training data and apply what it has learned to, ultimately, accelerate tape-outs and achieve PPA targets. Another key advantage of AI is its support of reuse: the retained learnings gained for one project can be utilized for future projects, bringing greater efficiency into the design process. Since the solution is available in the cloud, customers can take advantage of greater flexibility, scalability, and elasticity for massive workloads. Users have reported productivity enhancements of more than 3x, power reductions of up to 15%, and substantial die size reductions. Figure 1 shares results from the application of DSO.ai in a high-performance data center CPU.

VSO.ai Streamlines Last-Mile Efforts

VSO.ai helps verification engineers reach coverage closure targets faster and find more bugs. The number of design state spaces in which a digital design can operate is nearly infinite, making it virtually impossible for humans to check each of these spaces to validate that the design will function as intended. The regression process could run for days, eating up compute resources through thousands of tests. Often, the last mile closure ends up being very labor intensive, with manual analysis on huge amounts of data limited in yielding actionable insights.

VSO.ai revitalizes this process, examining the RTL to infer coverage while also highlighting areas where coverage is needed, saving substantial time and ensuring a high ROI on the tests. Renesas reports achieving up to 10x improvement in reducing functional coverage holes and up to 30% increase in IP verification productivity using AI-driven verification with Synopsys VCS® functional verification solution, a part of Synopsys.ai.

Conversely, someone with a lot of experience may have biases that cause him/her to set up the tool to achieve a certain result, which may not prove optimal for a new design. TSO.ai eliminates the tradeoffs, running multiple copies of Synopsys TestMAX™ ATPG advanced test solution to automate test program generation for enhanced defect coverage, fewer test patterns, and faster time to results.