HELPING YOU DESIGN THE CHIP INSIDE
Products and Solutions
---------- SOLUTIONS ----------
Eclypse Low Power Solution
Galaxy Design Platform
Design for Low Power
Design for Test
Design for Yield
RTL Synthesis
Physical Implementation
Sign-Off
Liberty CCS
SDC
Milkyway
Discovery Verification Platform
Analysis and Debug Tools
Low-Power Verification
System Analysis & Design
Smart RTL Verification
Functional Equivalence Checking
Mixed-Signal
Languages
Intellectual Property (IP)
DesignWare Library
DesignWare Verification IP
DesignWare Cores
DesignWare Star IP
DesignWare Foundry Libraries
IP Reuse Tools
Design for Manufacturing
Design-Yield Analysis
Mask Synthesis
Mask Data Preparation
Lithography Verification
TCAD
Manufacturing Yield Management
Professional Services
Tool and Methodology Deployment
Pilot Design Environment
Flow Optimization
Implementation
Verification Consulting
Concept to Parts
Core Hardening
---------- PRODUCTS ----------
BSD Compiler: Test synthesis
Cadabra: Cell creation
Calibration Library
CATS: Mask data preparation
Circuit Explorer: Analysis & Optimization
coreAssembler
coreBuilder
coreConsultant
CosmosLE: Layout design environment
CosmosScope: Waveform analysis
CosmosSE: Schem. design environment
DC Ultra: RTL synthesis
Design Analyzer: RTL synthesis
Design Compiler: RTL synthesis
DesignWare: Design & verif. IP
DesignWare Virtual Platforms
DFT Compiler MAX
DFT Compiler: Test synthesis
DSSA Sentry
Enterprise: Layout editor
ESP: Transistor-level Equivalence Checking
Formality: Funct. equiv. checking
Hercules: Physical verification
HSIM
HSPICE: Accurate circuit simulation
IC Compiler
IC Workbench
Innovator: SoC / system modeling
JupiterXT: Design planning
Leda: RTL checker
Library Compiler: Library compilation
Liberty NCX: CCS Characterization
Magellan: RTL formal verification
Memory Solution
Milkyway: Design database
MVRC
MVSIM
NanoChar: 90 nanometer & below characterization
NanoSim: Fast circuit simulation
NanoTime
Odyssey Defect/Odyssey YMS
Paramos
Pilot Design Environment
Pioneer-NTB: SystemVerilog testbench automation
Power Compiler: Power optimization
PrimePower: Power analysis
PrimeRail
PrimeTime PX
PrimeTime: Static timing analysis
PrimeTime SI: Signal integrity analysis
PrimeYield Tool Suite
Proteus OPC
PSM-Create & PSM-Check
Raphael
Raphael NXT
Recipe Manager and Editor (RME)
Saber: Multi-tech. simulation
Scirocco: VHDL simulation
Seismos
Sentaurus Device
Sentaurus Lithography
Sentaurus Process
Sentaurus Structure Editor
Sentaurus TFM
Sentaurus Topography
Sentaurus Workbench
SiVL-LRC: Lithography verification
SpiceCheck
SpiceExplorer
Star-RCXT: Full-chip RC extraction
Star-RCXT VX
Star-SimXT: Fast circuit simulation
System Studio: DSP algorithm design
Taurus-Medici
Taurus-TSuprem4
TetraMAX: ATPG
VCS: Comprehensive RTL Verification
VCS MX: Mixed-HDL simulation
Vera: Testbench automation
WaveView Analyzer
DESIGN IMPLEMENTATION
VERIFICATION
INTELLECTUAL PROPERTY
DFM/TCAD
DESIGN SERVICES
HSPICE INTEGRATOR PROGRAM
MEMBERS BENEFITS
READY TO JOIN!
CONTACT US
HSPICE Integrator Program - Membership Proposal Form
Contact Us
Please provide the following information. All fields with a
are required.
First Name
Last Name
Job Title
Company
Address
City
State
Postal/Zip Code
Phone Number
Fax Number
Email Address
Who will be the main contacts at your site? Please provide both a marketing and technical contact.
Please provide an overview of your company and product information.
Which
HSPICE-related
Synopsys tools do you expect will become part of the interoperability flow?
Please include reasons why access to the tool is required.
Which of your company's tools will become part of the interoperability flow?
For each of your company’s tools, please provide estimated time needed to complete interface with HSPICE-related tools from Synopsys.
How will customers benefit from this interoperability flow?
How will this relationship benefit both Synopsys and your company?
Please provide a detailed technical description (including data formats) of the proposed interoperability flow. A flow diagram will be required at a later date.
Who are the common customers requesting the joint flow?
The in-Sync team may contact these customers to ensure the need for the proposed joint solution. Please verify customer willingness to provide feedback when contacted by in-Sync before you volunteer them.
For each customer, include a company name, a contact person, title, division, address, phone, fax, and email address. This information is confidential to the in-Sync program and its Executive Board, and will be used solely for the purpose of verifying and justifying customer demand for the proposed joint flow(s) (please see in-Sync Program Overview)
If you are not comfortable providing this information here, you can email it to
insync@synopsys.com
or
fax to (650) 584-4102.
"Synopsys reserves the right to refuse in-Sync membership to any applicant involved in litigation with Synopsys or against whom Synopsys determines it has an actual or potential legal claim, including but not limited to patent infringement or misappropriation of intellectual property or unpaid and overdue accounts payable."
PERSONAL INFORMATION USE:
Synopsys will not share your personal information with anyone unless it obtains your prior approval. Synopsys may, however, provide aggregate market research data to other organizations as well as share the information you provide to Synopsys worldwide subsidiaries and business partners.
By registering, you agree to the terms of the Synopsys
Privacy Policy
.
CONTACT US
|
FEEDBACK
|
LOCATIONS
|
PRIVACY POLICY
|
LEGAL
© 2008 Synopsys, Inc. All Rights Reserved.