Design for power at the system-level has a dramatic impact on the ability to deliver low power, high performance platforms for mobile applications. There are multiple levels at which power optimization happens during system-level design. At a macroscopic level designers can optimize the platform architecture for overall system throughput of the memory and interconnect architecture. This will determine the amount of power consumption caused by data movements between multiple processors, hardware accelerators, interface blocks as well as on-chip and off-chip memories.
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