SNUG Boston 2013 Proceedings

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Complete Proceedings


User Papers and Presentations
A1 User Paper Session - Advanced Verification Techniques
Managing Verification of Highly Parameterized Designs
Author(s): Joe Manzella, Rich Peachey - LSI
PaperPresentation

Who's Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your Verification Environment
Author(s): David Brownell - Analog Devices, Inc.
PaperPresentation

A2 User Paper & Tutorial Session - Coverage Closure and other Verification Topics
Coverage Closure and Debug Using Symbolic Simulation (2nd Place - Best Paper)
Author(s): Courtney Schmitt - Analog Devices, Inc.; Manoharan Vellingiri, Alex Wakefield - Synopsys
PaperPresentation

Covering the Gap: A Tutorial on Coverage-Driven Verification Methodology
Author(s): Kurt Schwartz - Willamette HDL, Inc.
PaperPresentation

Making the Most of SystemVerilog and UVM - Hints and Tips for New Users
Author(s): Dr. Christopher Suehnel, Dr. David Long - Doulos
PaperPresentation

A3 User Paper Session - UVM Based Verification Techniques
Considerations for Development and Support of Exportable UVM IP
Author(s): Steven K. Sherman – Advanced Micro Devices
PaperPresentation

Getting Around the UVM "One Test-top Approach"
Author(s): Anshul Dhingra, Nithin Nagar Dhruvanarayan, Dave Workman - Advanced Micro Devices
PaperPresentation

C1 User Paper & Tutorial Session - Frontend Implementation - Multi-Voltage Design Verification and Formality Ultra
Successful Multi-Voltage Design: Using Power-aware Equivalence Checking and Static MV Analysis to Boost Tape-out Confidence (1st Place - Best Paper, Technical Committee Award)
Author(s):
PaperPresentation

C2 User Paper & Tutorial Session - Frontend Implementation: Optimization
Applying DOE to Logic Synthesis and Placement
Author(s): Ethan Bancala - Advanced Micro Devices
PaperPresentation

D1 User Paper & Tutorial Session - Plug In and Sign Off - Physical Verification Within IC Compiler
Conquering First 20nm Tapeout Challenges with IC Compiler and IC Validator
Author(s): Scott McCloskey - Qualcomm; Amzie Adams - Synopsys
PaperPresentation

D2 Tutorial & User Paper Session - Taking Your Design Skills to the Next Level
Application of the Multisource CTS Operative in IC Compiler
Author(s): Ryan Helfand - Advanced Micro Devices
PaperPresentation

E1 User Paper & Tutorial Session - Advanced Test Techniques
Placement Based Analysis of Scan Test ATPG Results
Author(s): Glenn Boyer - Synopsys, Kelvin Ge - Samsung
PaperPresentation

E3 User Paper & Tutorial Session - Static Timing
Timing Verification for CDC Paths in Large-scale SoCs
Author(s): Sambasivan Narayan, Michael Tresidder - Advanced Micro Devices
PaperPresentation

F1 User Paper & Tutorial Session - Transistor-level Static Timing
Accurate Timing of Dynamic Circuits Using NanoTime Static Timing Analysis
Author(s): Meghna Singha, Timothy Correia, Yaping Zhan, Stephen Lim, David Newmark - Advanced Micro Devices; Norb Heindl, Paul Collins - Synopsys
PaperPresentation

F2 User Paper & Tutorial Session - Custom Design and Layout
Corner Wiring and Via Placement Made Easy in Custom Designer Layout Editor (2nd Place - Best Paper)
Author(s): James Cherry - Kapik Inc.
PaperPresentation

Publication Only
Publish Only
Automated Testbench for Coverage Closure
Author(s): Anshul Dhingra, Dave Workman, Nithin Nagar - Advanced Micro Devices
Paper

SDMLp Standard Cell Library Generation using Synopsys Custom Designer, Liberty NCX & Milkyway Tools
Author(s): Antarpreet Singh Manchanda, Mike Borowczak, Dr.Ranga Vemuri - University of Cincinnati
Paper

Verifying Full Node Traversal With NanoTime
Author(s): Dan Hartman, Vasu Kandadi - Cavium Networks
Paper

Tutorials
B1 Tutorial Session - Advanced FPGA Implementation
Designing with Xilinx 7 Series FPGAs
Author(s): Steve Gercken - Synopsys
Tutorial

Integrating Custom Logic in SoC FPGAs
Author(s): Andy Lee - Arrow/Altera Corporation
Tutorial

B2 Tutorial Session - FPGA Prototyping and Verification
Formal Verification of FPGAs
Author(s): Gene Stuckey - Synopsys
Tutorial

Using FPGA-based Prototyping Systems for M-PCIe System Development
Author(s): Peter Calabrese - Synopsys
Tutorial

Verifying Low Power ASIC Design Specification (UPF) via FPGA Prototyping
Author(s): Carl Cleaver - Synopsys
Tutorial

B3 Tutorial Session - System Implementation and Verification
Application-Specific Processor Design and Prototyping
Author(s): Drew Taussig - Synopsys
Tutorial

Complex SoC Prototyping Using Xilinx Virtex-7-Based HAPS-70 Systems
Author(s): Andy Jolley - Synopsys
Tutorial

C1 User Paper & Tutorial Session - Frontend Implementation - Multi-Voltage Design Verification and Formality Ultra
Advanced Debugging Features of Formality Ultra
Author(s): Steve Lamb - Synopsys
Presentation

C2 User Paper & Tutorial Session - Frontend Implementation: Optimization
DC Graphical Layer Optimization
Author(s): Chris Kennedy - Synopsys
Tutorial

What's New in Synthesis from R&D's Perspective
Author(s): Janet Olson - Synopsys

C3 Tutorial Session - Frontend Implementation: Test & Low Power
How Low Power Can You Go?
Author(s): John Geremia - Synopsys
Tutorial

Test it, Test it, You Want to Test it!
Author(s): Dave Chagnon - Synopsys
Tutorial

D1 User Paper & Tutorial Session - Plug In and Sign Off - Physical Verification Within IC Compiler
20nm Design Closure in ICC using IC Validator in-Design
Author(s): Chris Grossmann- Synopsys
Tutorial

D2 Tutorial & User Paper Session - Taking Your Design Skills to the Next Level
Employing Data Flow Analysis Techniques
Author(s): Tom Concannon - Synopsys
Tutorial

Engineering Trade-Offs in the Implementation of a High-Performance Dual-core ARM® Cortex™-A15 Processor
Author(s): Barry Spotts - ARM®, Darin Hauer - Synopsys
Presentation

Multisource CTS: Achieve Higher Frequencies for Your Design
Author(s): Dave Power - Synopsys
Tutorial

E1 User Paper & Tutorial Session - Advanced Test Techniques
Meeting Quality Goals for Gigascale Designs: Trends and Solutions (Part 1)
Author(s): Mona Marmash - Synopsys
Tutorial

E2 Tutorial Session - Improving Test
Debugging Low Test Coverage
Author(s): Mona Marmash - Synopsys
Tutorial

Meeting Quality Goals for Gigascale Designs: Trends and Solutions (Part 2)
Author(s): Tim Yuan - Synopsys
Tutorial

E3 User Paper & Tutorial Session - Static Timing
PrimeTime Advance Topics and Flows
Author(s): Bob Grozier - Synopsys
Tutorial

F1 User Paper & Tutorial Session - Transistor-level Static Timing
Differential Full-swing Static Timing Analysis Enhancements to NanoTime
Author(s): Maureen Ladd, Synopsys
Tutorial

F2 User Paper & Tutorial Session - Custom Design and Layout
Laker3 Custom Layout System - " An Advanced Process Node Layout Tutorial"
Author(s): Janet Talamentez - Synopsys
Tutorial

F3 Tutorial Session - FinFET Transistor-level Extraction and Simulation
BSIM-CMG FinFET Model Complexity and its Impact on Synopsys AMS Simulation
Author(s): Bob Williams - Synopsys
Tutorial

StarRC Transistor-level Extraction: Optimizing Accuracy and Performance for Custom AMS Flows and sub-20nm Technologies
Author(s): Synopsys
Tutorial