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| Tutorials |
| MA2 Tutorial & User Session: Custom Designer Accelerators and Revision Control |
Using Custom Designer Accelerators to Speed-up your Design Cycle
Author(s): Nic Regis (Synopsys, Inc.) |
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| MA3 Tutorial Session: Signoff Driven Design Closure, and Route Correlation |
ECO Timing Closure: Fast and Flexible Multi-Scenario DRC Fixing
Author(s): Pervinder Trehan (Synopsys, Inc.) |
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Intelligent and Automated Layer-Aware Pre-Route Optimization for Improved Post-Route Correlation for Advanced Technology Nodes
Author(s): Eric Antognelli (Synopsys, Inc.) |
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| MA4 User and Tutorial Session: Test Coverage and Design Exploration |
Synopsys DC Explorer and 2012.06 Design Compiler Highlights
Author(s): Bob Wiegand (Synopsys Inc.) |
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| MB1 Tutorial & User Session: DVE and Low Power Verification |
Live Demo: Debugging UVM testbench and Constraint with DVE
Author(s): Jason Chen (Synopsys, Inc.) |
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| MB2 Tutorial Session: Preventing Electromigration and ERC/ESD |
An Automated Method for Avoiding Electromigration Failures During Layout Creation
Author(s): Faisal Saleh (Synopsys, Inc.) |
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IP Validator
Author(s): Glen Hertz (Synopsys, Inc.) |
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| MB3 Tutorial Session: Top Level Closure and Multi-IO Ring Design |
Creating Multi-IO Ring Die Using IC Compiler
Author(s): Sufyan Khan (Synopsys, Inc.) |
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Faster Top Level Closure With Transparent Interface Optimization (TIO)
Author(s): Jim Lehman (Synopsys, Inc.) |
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| MB4 Tutorial Session: ECO Timing Closure & PrimeTime/PrimeTime SI |
ECO Timing Closure: Fast and Flexible Multi-Scenario DRC Fixing
Author(s): Pervinder Trehan (Synopsys, Inc.) |
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PrimeTime/PrimeTime-SI 2011/2012 Special Topics and Methodology
Author(s): Paul Lamers (Synopsys, Inc.) |
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| MC2 Tutorial Session: Advanced Interactive Debugging Utilities in ICV |
Advanced Interactive Debugging Utilities in ICV
Author(s): Tim Guttormson (Synopsys, Inc.) |
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| MC3 Tutorial Session: High Performance Cores and 20nm Design Success |
IC Compiler: Achieving Design Success at 20nm
Author(s): Sufyan Khan (Synopsys, Inc.) |
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Techniques for High Performance Cores using Synopsys Galaxy Platform-ARM® Cortex-A15 Case Study
Author(s): Daniel Biset (Synopsys, Inc.) |
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| MC4 User & Tutorial Session: Constraint Analysis |
Minimizing Risk in Multi-Clock Designs with GCA
Author(s): Mark DiGiovanni (Synopsys Inc.) |