SNUG Canada 2012 Proceedings

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Complete Proceedings


User Papers and Presentations
MA1 User Session: Reuse and Methodology
A Mechanism for Hierarchical Reuse of Interface Bindings
Author(s): Thomas Zboril (Qualcomm Atheros)
PaperPresentation

Developing a Re-Use Base Layer with UVM
Author(s): Pierre Girodias (IDT)
PaperPresentation

Top-Down vs. Bottom-Up Verification Methodology for Complex ASICs
Author(s): Paul Lungu, Zygmunt Pasturczyk (Ciena)
PaperPresentation

MA2 Tutorial & User Session: Custom Designer Accelerators and Revision Control
Integrating SVN Revision Control Software with Synopsys Custom Designer (1st Place - Best Paper)
Author(s): James Cherry (Kapik Integration)
PaperPresentation

MA4 User and Tutorial Session: Test Coverage and Design Exploration
I Upped My Coverage, Up Yours! (Technical Committee Award)
Author(s): Martin Salomon (STMicroelectronics, Inc.)
Paper

MB1 Tutorial & User Session: DVE and Low Power Verification
Insight Into Power Gating Verification (3rd Place - Best Paper)
Author(s): Ashwini Chandrashekhara Holla (Advanced Micro Devices)
PaperPresentation

MC1 User Session: Stimulus Generation, Constraint Random and Error Injection
A Perspective on Soft and Default Constraints (2nd Place - Best Paper)
Author(s): Karim Khordoc (Cisco Systems); Jason Chen (Synopsys, Inc.);
Paper

UVM Sequence Item Based Error Injection
Author(s): Jeffrey Montesano, Mark Litterick (Verilab)
PaperPresentation

Verification of a Custom RISC Processor
Author(s): Andrew Elms (Huawei Canada);
PaperPresentation

MC4 User & Tutorial Session: Constraint Analysis
Reducing STA Constraints Churn Using GCA
Author(s): Brian Silveira (Huawei Canada)
PaperPresentation

Publication Only
Disciplined Design Documentation Dextrously Done with UML
Author(s): Bryan Morris (Verilab)
Paper

Tutorials
MA2 Tutorial & User Session: Custom Designer Accelerators and Revision Control
Using Custom Designer Accelerators to Speed-up your Design Cycle
Author(s): Nic Regis (Synopsys, Inc.)

MA3 Tutorial Session: Signoff Driven Design Closure, and Route Correlation
ECO Timing Closure: Fast and Flexible Multi-Scenario DRC Fixing
Author(s): Pervinder Trehan (Synopsys, Inc.)

Intelligent and Automated Layer-Aware Pre-Route Optimization for Improved Post-Route Correlation for Advanced Technology Nodes
Author(s): Eric Antognelli (Synopsys, Inc.)

MA4 User and Tutorial Session: Test Coverage and Design Exploration
Synopsys DC Explorer and 2012.06 Design Compiler Highlights
Author(s): Bob Wiegand (Synopsys Inc.)

MB1 Tutorial & User Session: DVE and Low Power Verification
Live Demo: Debugging UVM testbench and Constraint with DVE
Author(s): Jason Chen (Synopsys, Inc.)

MB2 Tutorial Session: Preventing Electromigration and ERC/ESD
An Automated Method for Avoiding Electromigration Failures During Layout Creation
Author(s): Faisal Saleh (Synopsys, Inc.)

IP Validator
Author(s): Glen Hertz (Synopsys, Inc.)

MB3 Tutorial Session: Top Level Closure and Multi-IO Ring Design
Creating Multi-IO Ring Die Using IC Compiler
Author(s): Sufyan Khan (Synopsys, Inc.)

Faster Top Level Closure With Transparent Interface Optimization (TIO)
Author(s): Jim Lehman (Synopsys, Inc.)

MB4 Tutorial Session: ECO Timing Closure & PrimeTime/PrimeTime SI
ECO Timing Closure: Fast and Flexible Multi-Scenario DRC Fixing
Author(s): Pervinder Trehan (Synopsys, Inc.)

PrimeTime/PrimeTime-SI  2011/2012 Special Topics and Methodology
Author(s): Paul Lamers (Synopsys, Inc.)

MC2 Tutorial Session: Advanced Interactive Debugging Utilities in ICV
Advanced Interactive Debugging Utilities in ICV
Author(s): Tim Guttormson (Synopsys, Inc.)

MC3 Tutorial Session: High Performance Cores and 20nm Design Success
IC Compiler: Achieving Design Success at 20nm
Author(s): Sufyan Khan (Synopsys, Inc.)

Techniques for High Performance Cores using Synopsys Galaxy Platform-ARM® Cortex-A15 Case Study
Author(s): Daniel Biset (Synopsys, Inc.)

MC4 User & Tutorial Session: Constraint Analysis
Minimizing Risk in Multi-Clock Designs with GCA
Author(s): Mark DiGiovanni (Synopsys Inc.)