SNUG France 2012 Proceedings

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Complete Proceedings

Speeches
Welcome and Keynote Address
Author(s): Aart de Geus, Synopsys CEO & Chairman of the Board, Joachim Kunkel, Sr. Vice President and General Manager [Synopsys Solutions Group]

User Papers and Presentations
A1 User Session: Front-to-Back Implementation
Advanced Design Flow for LPDDR2 non Volatile Memory Design (Technical Committee Award)
Author(s): Anna Faldarini, Christophe Laurent [Micron Technology]
PaperPresentation

Advanced Design Flow: Design of a Full-HD120 Video Accelerator from a C Architecture to an ICC Implementation
Author(s): Alexandre Bleys [ST-Ericsson]
PaperPresentation

Design Optimization and Formal Checking with Retiming Techniques (Technical Committee Award Honorable Mention)
Author(s): Philippe Maneta [ST-Ericsson]
PaperPresentation

A2 User Session: Low-Power Verification
Dynamic Low-Power Verification on a Multi-CPU Subsystem using VCS-NLP
Author(s): Massimo Calligaro [ST-Ericsson]
PaperPresentation

Formal and Low-Power Verification on Large SoC Designs
Author(s): Yassine EL Khourassani [ST-Ericsson]
PaperPresentation

Real Voltage Modeling through Assertions (2nd Place - Best Paper)
Author(s): Ankita Arya, Mohit Jain, Chandan Singh [STMicroelectronics]
PaperPresentation

A3 User & Tutorial Session: Hierarchical Design & Floorplanning
Hierarchical Design-Planning of a Multi-million Instance Design
Author(s): Rashid Iqbal [Intel]
PaperPresentation

ICC Template-Based Power Network Synthesis (TPNS) & Power Network Analysis (PNA) to Increase Implementation and Verification Efficiency of Mixed-Signal Design Multi-Voltage Power Ground Grids
Author(s): Christelle Leherpeur [STMicroelectronics]
PaperPresentation

A4 User Session: Design for Test and ATPG I
Early Power Analysis Methodology using PrimeTime PX to Assess Achievable Maximum Shift Frequency before ATPG
Author(s): Jean-Michel Lagoutte [ST-Ericsson], Philippe Rossant [Synopsys France]
PaperPresentation

State-of-the-Art, Low-Power DFT Methodology
Author(s): Swapnil Bahl, Shray Khullar, Roberto Mattiuzzo, Saverio Graniello [STMicroelectronics]
PaperPresentation

Using TetraMax Top Level Protocol Generation to Extract DFTMAX Codec Information for Lifetest Pattern Generation (HTOL) (3rd Place - Best Paper)
Author(s): Gerald Briat, Stéphane Guilhot [ST-Ericsson], Philippe Rossant [Synopsys]
PaperPresentation

A5 User and Tutorial Session: FPGA Implementation
Implementing Dual Role Device USB2/3 IP from Synopsys using the HAPS6x Platform
Author(s): Nicolas Krohmer [Texas Instrument]
PaperPresentation

A6 User Session: AMS Verification and Sign-off
Case Study: Correlating PrimeTime with SPICE
Author(s): Casey McCoy [Atmel Corporation]
PaperPresentation

Groundbreaking SQL Method to Analyze Circuit Check Reports
Author(s): Pierluigi Daglio, Salvatore Santapa, Alessandro Valerio [STMicroelectronics]
PaperPresentation

Methodology for ST NVM Technologies Description Turned to Interconnect Parasitic Extraction with StarRC and to the Memory Cell Characterization with Rapid3D
Author(s): Marina Gratarola, Silvia Lesma, Luca Togni [STMicroelectronics], Claudio Rallo [Synopsys]
PaperPresentation

B2 User & Tutorial Session: Testbench and Verification IP
A Beginner’s Guide to Using SystemC TLM-2.0 IP with UVM
Author(s): John Aynsley, David Long, Doug Smith [Doulos]
PaperPresentation

B3 User and Combo Session: Clock Tree Synthesis & Sign-off
Asic Compliance CTMesh Solution
Author(s): Boon Chong Ang, Phooi Choong Loh [Intel]
PaperPresentation

B4 User & Tutorial Session: Design for Test and ATPG II
Efficient Flow for the Debug of Compressed Scan Patterns During Serial Simulations (1st Place - Best Paper, Best Paper Award)
Author(s): Sébastien Rousset, Mathieu Thomas [Scaleo Chip]
PaperPresentation

B5 User White Paper and Tutorial Session: Advanced FPGA Design Techniques
FPGA Hierarchical Design Techniques using Synopsys SynplifyPremier and Xilinx PlanAhead
Author(s): James McLenaghan [Xilinx], Xavier Mathes [Synopsys]
PaperPresentation

B6 User and Tutorial/Demo Session: Digital/Analog Co-Design
Bridging the Digital/Analog Gap in Design Implementation
Author(s): Giuseppe Conti [STMicroelectronics], Giuseppe Contarino [Synopsys Italy]
PaperPresentation

C1 User & Tutorial Session: RTL Synthesis
An All-Inclusive Solution for Clock Domain Crossings
Author(s): Charles Laurent, Phuong Nguyen, Joseph Dekoker, Domenique Spagnuolo [Sigma Designs]
PaperPresentation

C3 User & Tutorial Session: Design Closure
Implementing an High-Performance Graphic Core with Synopsys Galaxy Platform in a Fast and Predictable Turnaround Time
Author(s): Pascal Teissier [STMicroelectronics]
PaperPresentation

C4 User, Tutorial and R&D Session: Advanced Test Techniques
Custom LBIST Integration in an Automotive Design
Author(s): Marzia Annovazzi, Marcello Raimondi [STMicroelectronics]
PaperPresentation

Tutorials
A3 User & Tutorial Session: Hierarchical Design & Floorplanning
Faster Top-Level Closure with Transparent Interface Optimization (TIO)
Author(s): Gaspard Thaller [Synopsys]
Tutorial

A5 User and Tutorial Session: FPGA Implementation
Standard SDC & Clock Issues in Complex FPGA Designs
Author(s): Laurent Sol, Xavier Mathes [Synopsys France]
Tutorial

B1 Tutorial Session: Front-End IP Integration
Best Practices for Implementing Memories and Libraries to Deliver Superior PPA and Embedded Test & Repair
Author(s): Zaka Bhatti [Synopsys, Inc.]
Tutorial

Galaxy Constraints Analyzer Intro, Update & Demo
Author(s): Emmanuel Pluchart [Synopsys France]
Tutorial

B2 User & Tutorial Session: Testbench and Verification IP
Accelerated SoC Verification with Synopsys Discovery VIP for the ARM AMBA 4 ACE Protocol
Author(s): Chris Thompson [Synopsys Canada]
Tutorial

B3 User and Combo Session: Clock Tree Synthesis & Sign-off
PrimeTime Usability Update & Multi-Scenario DRC Fixing
Author(s): Eric Zann [Synopsys France]
Tutorial

B4 User & Tutorial Session: Design for Test and ATPG II
Galaxy Test Update
Author(s): Jean-Pierre Popieul [Synopsys France]
Tutorial

B5 User White Paper and Tutorial Session: Advanced FPGA Design Techniques
New Synopsys Implementation Flow for Xilinx Series 7
Author(s): Xavier Mathes [Synopsys]
Tutorial

Synopsys Cookbook to Reduce Congestion on Virtex6 Designs
Author(s): Laurent Sol [Synopsys France]
Tutorial

B6 User and Tutorial/Demo Session: Digital/Analog Co-Design
Digital/Analog Co-design with IC Compiler and Custom Designer
Author(s): Guillaume Thomas [Synopsys]
Tutorial

C1 User & Tutorial Session: RTL Synthesis
Galaxy RTL: Design Compiler Family Update
Author(s): Alberto Baldi [Synopsys]
Tutorial

C2 Combo and Tutorial Session: Core Simulation
Getting X propagation under Control
Author(s): Roger Ninane [Synopsys]
Tutorial

VCS Technologies and Testbench Methodologies for Achieving Higher Video Throughput
Author(s): Fabian Delguste [Synopsys]
Tutorial

C3 User & Tutorial Session: Design Closure
Optimized Implementation for High Performance Cores: Techniques for High Performance Cores Using Synopsys Galaxy Platform - ARM® Cortex™-A15 Case Study
Author(s): Herve Raffard [Synopsys]
Tutorial

C4 User, Tutorial and R&D Session: Advanced Test Techniques
Introduction to the Synopsys DesignWare STAR Memory System (SMS)
Author(s): Steven Oostdijk [Synopsys]
Tutorial

R&D Session: Core Wrapping
Author(s): Frederic Neuveux [Synopsys]
Tutorial

C5 Tutorial & Demo Session: Custom Processors & Design Verification using FPGA Platforms
Debug and Functional Verification using Latest Identify Features
Author(s): Laurent Sol [Synopsys]
Tutorial

Programmable Hardware Accelerators made Easy: Rapid Prototyping of Custom Processors on HAPS without Compromising Performance, Power or Area
Author(s): Xavier Buisson [Synopsys]
Tutorial

C6 Tutorial Session: Analog IPs & Circuit Simulation
How to Get the Most from Your Circuit Simulation
Author(s): Beatrice Solignac [Synopsys]
Tutorial

The Evolving Integrated Communication AFE
Author(s): Manuel Mota [Synopsys]
Tutorial