SNUG India 2013 Proceedings

Speeches
Keynote Address
The Role of Intelligent Silicon in Addressing Data Deluge Gap
Author(s): Raman Santhanakrishnan - LSI India R&D Pvt Ltd
Keynote

Keynote Address
Massive Innovation and Collaboration into the "GigaScale" Age!
Author(s): Aart de Geus, Chairman and co-CEO - Synopsys, Inc.

User Papers and Presentations
TB1: Synopsys Tutorial Sessions
TB1.1 Tutorial: Addressing Low Power Verification Challenges with VCS
Author(s): Synopsys
Tutorial

WA1: Synopsys User and Tutorial Sessions
WA1.3 User Paper: Innovative Approach to Overcome Limitations of Netlist Simulation (Outstanding Technical Paper Award)
Author(s): Prodip Kundu, Pankaj Singh, Narendran Kumaragurunathan, Meera Mohan - AMD India Pvt. Ltd
PaperPresentation

WC2: Synopsys User Session
WC2.2 User Paper: Dynamic Electrical Rule Checking (ERC) Capability in FineSim to Avoid Hot-Spots & Achieve Low-Power Specification
Author(s): Mithun Kumar, Ashwin Nyamati - Microchip Technology India Pvt Ltd, Vivek Sharma - Synopsys
PaperPresentation

WC2.3 User Paper: EMI & SSO simulation on board: Modelling, Analysis, And Design Solutions
Author(s): Akhilesh Mishra, Prabhat Ranjan,Yagya Dutt Mishra - STMicroelectronics
PaperPresentation

Publication Only
Co-Simulation - An effective technique to optimise Simulation Speed
Author(s): Jayashri Abm, Shishira M Pareppady, Ray Schuppe, Priya Ananthakrishnan, Vijay Bagalad - IBM
Publish Only

Dynamic Power Reeduction Using XOR Self-clock Gating Methodology
Author(s): Shinoj A Balakrishnan, Varada Prasad Y A - Intel
Publish Only

Dynamic Template C eation Using ICV for Physical Design Methodology Checking
Author(s): Anand Kumaraswamy, Pardeep Saini, Harshit Agnihotri - IBM
Publish Only

Embedded Memories and Readiness of ESP-CV for 20nm and Beyond
Author(s): Prakhar Raj Gupta, Rashna Seli -ST Microelectronics, Rakesh Shenoy - Synopsys
Publish Only

Methodology for signoff convergence and smooth SoC integration of high performance partition
Author(s): Anuj Soni, Kumud Kakati. Prashant Sharma. Shrinivas Sureban - LSI Technologies
Publish Only

Scalable, Configurable, Reusable (SCORE) Test Bench Using UVM & Advance Debugging Techniques Using DVE
Author(s): Peer Mohammed, Naveen Yanamadala, Vinay Kumar Vedula - Mindspeed, Parag Goel - Synopsys
Publish Only

SystemC / TLM model of Audio Codec
Author(s): Parvinder Pal Singh, Shabarish Sundar, Archna Verma, Umesh Sisodia - CircuitSutra Technologies
Publish Only

Timing Report Pyramid – Something for Everyone
Author(s): Tripurasundari Sundaresh, Lisha Krishnan, Shankar N. Pushpendra Yadav - Cypress Semiconductor
Publish Only

Tutorials
TA1: Synopsys User and Tutorial Sessions
TA1.1 Tutorial: Design with FinFET & Double-Patterning, a Brief History of the Future
Author(s): Synopsys

TA3: High-Performance Cores
TA3.3 Tutorial: Engineering Trade-Offs in the Implementation of a High-Performance Dual Core ARM® Cortex™-A15 Processor
Author(s): ARM and Synopsys
Presentation

TB1: Synopsys Tutorial Sessions
TB1.2 Tutorial: Transaction Level Verification with Zebu Server
Author(s): Synopsys
Tutorial

TB2: Synopsys Tutorial Session
TB2.1 Tutorial: Advanced Verification Debug Productivity with Verdi3 and Siloti
Author(s): Synopsys
Tutorial

TB3: Synopsys Tutorial Session
TB3.1 Tutorial: Certitude for Functional Qualification
Author(s): Synopsys
Tutorial

TB3.2 Tutorial: VCS Technologies for Improved Performance and Productive Analysis
Author(s): Synopsys
Tutorial

TC1: Synopsys User and Tutorial Sessions
TC1.1 Tutorial: Low Power Video Processing for the Mobile SoC: How Analysis of HW-SW Partitioning Gets the Most from Embedded GPUs
Author(s): Synopsys
Tutorial

TC2: Synopsys User Session
TC2.1 Tutorial: Designing IP for FinFET Technology: The Opportunities and Challenges
Author(s): Synopsys
Tutorial

TC3: Synopsys User and Tutorial Session
TC3.1 Tutorial: Ease Debug and Control of Network Software using Virtual Prototypes to do Full System Simulation
Author(s): Synopsys
Tutorial

TD1: Synopsys User and Tutorial Sessions
TD1.3 User Paper: Handling Nested Power Domains in Complex SoC
Author(s): Shashank Bhonge, Vaishali Huilgol, Vinod Kumar Reddy - Xilinx
PaperPresentation

TD1.4 Tutorial: Unlocking the Low Power Potential of your Chip – An Advanced Flow Methodology using UPF2.0
Author(s): Synopsys
Tutorial

WA1: Synopsys User and Tutorial Sessions
WA1.1 Tutorial: Zebu Overview, Easier HDL Cosim, Productivity Techniques
Author(s): Synopsys
Tutorial

WB1: Synopsys User and Tutorial Sessions
WB 1.3 Tutorial: PrimeTime - Key Technologies and Release Updates
Author(s): Synopsys
Tutorial

WB2: Synopsys User Session
WB2.3 Tutorial: Handling of Advanced Technology and Process Challenges in Parasitic Extraction using StarRC
Author(s): Synopsys
Tutorial

WB3: Synopsys User and Tutorial Session
WB3.3 Tutorial: Mode Merging using PrimeTime-GCA
Author(s): Synopsys
Tutorial

WC1: Synopsys User and Tutorial Sessions
WC1.1 Tutorial: Laker Custom Layout System - "An Advanced Process Node Custom Layout Tutorial"
Author(s): Synopsys
Tutorial

WC3: Synopsys User and Tutorial Session
WC3.2 Tutorial: Characterizing Memories and Black Boxes: Belling the Cat
Author(s): Mohamed Filzer Kummudiyil - Synopsys
Tutorial

WD1: Synopsys User and Tutorial Sessions
WD1.2 User Paper: Effective ATPG with Hierarchical DFT Methodology for SoC
Author(s): Seema Shareef, Soham Roy, Ashwini Shankar - Wipro Technologies
PaperPresentation

WD1.4: New, Innovative Test Technology to Reduce the Cost of Quality
Author(s): Rohit Kapur - Synopsys
Tutorial

WD2: Synopsys User & Tutorial Session
WD2.1 Tutorial: The Essentials for an Integrated Synplify-Vivado Design Flow Targeting Xilinx 7 Series FPGAs
Author(s): Synopsys
Tutorial

WD3: User and Tutorial Session
WD3.3 Tutorial: My BFF FPGA-based Prototyping Solution: Better, Faster and Flexible
Author(s): Synopsys
Tutorial

User Presentation
TA1: Synopsys User and Tutorial Sessions
TA1.2 User Paper: Physical Design Challenges of a High-performance FPGA in 22nm Process Technology
Author(s): Aravind Karanth, Veena Radhakrishnan, Madhusudan Rajagopal, Namit Varma - Achronix Semiconductor Corporation
PaperPresentation

TA1.3 User Paper: Floorplanning is an ART and with DFA You are an Artist!!
Author(s): Hardeep Singh , Veena Venugopalan , Sarvesh Verma - LSI India Research and Development Pvt. Ltd.
PaperPresentation

TA2: Synopsys User Session
TA2.1 User Paper: Optimization Techniques for Designing a Channel Dominated High Activity Multimillion 500+Sq mm Chip
Author(s): Anurag Mishra - LSI R&D (India) Pvt. Ltd. Vineet Kumar Kothari - Synopsys
PaperPresentation

TA2.2 User Paper: In-Design 20nm Physical Verification Closure Within ICC Using ICV
Author(s): Siddika Gundlur, Hemasundar Pethakamsetty - AMD India Pvt Ltd.
PaperPresentation

TA2.3 User Paper: Multi-Pronged Approach to Address Nanometer Physical Verification Challenges (Outstanding Technical Paper Award)
Author(s): Mohamed Hassaly, Madan Lal, Veerakumar Pitchiah - Intel
Presentation

TA3: High-Performance Cores
TA3.1 User Paper: Synthesis Techniques for Faster Design Closure of High Performance Quad Core Processor
Author(s): Neha Agarwal , Kuldeep Chahal, Sagar Malhotra - STMicroelectronics Pvt Ltd.
PaperPresentation

TA3.2 User: GHz ++ : A Step by Step Tutorial on Recovering That Extra Picosecond
Author(s): Krishna Kant Verma - Qualcomm, Deepti Pookat - Synopsys
PaperPresentation

TC1: Synopsys User and Tutorial Sessions
TC1.2 User: Integration of Synopsys DesignWare DDR Controller & DDR3/2 PHY IP in 28nm
Author(s): Girish Karanam, Ashish Veeramaneni - Open-Silicon
Presentation

TC2: Synopsys User Session
TC2.2 User Paper: Synopsys Virtual Prototypes for Pre-Silicon Software Development - Texas Instrument’s Latest Experience
Author(s): Vishal Goel , Asiful Mondal - Texas Instruments, Mojin Kottarathil - Synopsys
PaperPresentation

TC3: Synopsys User and Tutorial Session
TC3.2 User Paper: Virtual Prototype for Infineon MCU Using Synopsys Virtualizer
Author(s): Prasanna Venkatesan Kesavan, Simranjit Singh - Infineon Technologies India Pvt Ltd., Indraneel Mondal, Prakash Sahay - Synopsys
Presentation

TD1: Synopsys User and Tutorial Sessions
TD1.1 User Paper: Dynamic Power Optimization Techniques for Highly Switching Design In Physical Implementation
Author(s): Devendra Deshpande, Shaibal Kavdia, Mayank Mittal - LSI India Pvt Ltd
PaperPresentation

TD1.2 User Paper: Efficient Methodology for Leakage Optimization with Synopsys Tools
Author(s): Jürgen Karmann, Ravikumar Rajendraprasad - Infineon Technologies India PVT Ltd.
PaperPresentation

TD2: Synopsys User & Tutorial Session
TD2.1 User Paper: Novel Low Power Static Checking Methodology now Integrated in MVRC (Outstanding Technical Paper Award)
Author(s): Neha Agarwal, Nitin Kaushik - STMicroelectronics Pvt Ltd, Patrick Blestel, Stephanie Varela - Synopsys
PaperPresentation

TD2.2 Tutorial: Next Generation Static Verification Platform (Verdi Signoff) - Low Power
Author(s): Synopsys
Tutorial

WA1: Synopsys User and Tutorial Sessions
WA1.2 User Paper: Zebu Transactors for Verification & Validation
Author(s): Karthikeyan Rajamanickam - Texas Instruments
PaperPresentation

WA2: Synopsys User Session
WA2.1 User Paper: X-Propagation - Improving the Methodology in Uncovering X-optimism Issues
Author(s): Ashish Gogia - Cisco Systems India, Shekhar Basavanna, Vasudev Srinivasan - Synopsys
PaperPresentation

WA2.2 User Paper: Certitude for Functional Safety
Author(s): Deva Phanindra Kumar,Ranganayakulu Sri - Analog Devices Inc.
PaperPresentation

WA2.3 User Paper: Reconfigurable Verification Environments with Discovery VIP & Reusable Test Cases Using SystemVerilog DPI
Author(s): Yugandhar Kadiry, Naresh Duriseti - Mindspeed Technologies, Viswanath Daita - Synopsys
PaperPresentation

WA3: Synopsys User Session
WA3.1 User Paper: AFE Verification - A Novel approach for Mixed Signal Verification
Author(s): Neeraj Chandak, Nitin Goel, Yogesh Mittal - Freescale Semiconductors India Pvt Ltd.
PaperPresentation

WA3.2 User Paper: Generic RAL Infrastructure to Address Register Verification Challenges
Author(s): Sreenivas Machavaram, Anil Kumar Sabbineni, Prashanth Srinivasa - LSI
PaperPresentation

WB1: Synopsys User and Tutorial Sessions
WB1.1 User Paper: Addressing Signoff Timing Quality and Cycle Time Challenges in High Performance Processor Designs
Author(s): Prashant Soraiyur - Intel
PaperPresentation

WB1.2 User Paper: Novel Approach to do Multi Voltage Signoff using SMVA
Author(s): Ish Chadha - NVIDIA
PaperPresentation

WB2: Synopsys User Session
WB2.1 User Paper: Handling Non-monotonic Delays in Static Timing Analysis
Author(s): Lisha Krishnan, Mohan Sultania, Debashis Sarkar - Cypress
PaperPresentation

WB2.2: TAT Improvement in Signoff Extraction using SMC Flows
Author(s): Gopinath Devarajan, Dan Prevedel - LSI
PaperPresentation

WB3: Synopsys User and Tutorial Session
WB3.1 User Paper: The Last Microwatt - Challenges in Pre Silicon Power Estimation for Low-Power SoCs
Author(s): Kaushik Saiprasad, Pooja Saseendran, Syed S Thameem - Intel
PaperPresentation

WB3.2 User Paper: Method for Collapsing Multiple Modes Timing Constraints (Outstanding Technical Paper Award)
Author(s): Rajkumar Agrawal, Vivek Manikandan LSI India Research & Development Pvt Ltd
PaperPresentation

WC1: Synopsys User and Tutorial Sessions
WC1.2 User Paper: FineSim for Complex Mixed-Signal SoC Verification
Author(s): Anmol Mahajan, Amit Kumar Singh, Karthik Sundararaj - Analog Devices, India, Vivek Sharma - Synopsys
PaperPresentation

WC1.3 User Paper: Custom Routing Flow Enablement for Advanced Nodes
Author(s): Indushekar Benjiwal, Bhupendra Vishwakarma - Intel
PaperPresentation

WC2: Synopsys User Session
WC2.1 User Paper: Determining PLL Clock Jitter Characteristics Using XA-VCS Mixed-Signal Simulations (Oustanding Technical Paper Award)
Author(s): Ratheesh Mekkadan - AMD
PaperPresentation

WC3: Synopsys User and Tutorial Session
WC3.1 User: On Chip Adaptive Voltage Scaling to Minimize Dynamic Current Consumption
Author(s): Kumar Abhishek, Sunny Gupta, Nitin Pant, Manmohan Rana - Freescale Semiconductors
PaperPresentation

WD1: Synopsys User and Tutorial Sessions
WD1.1 User Paper: Increase ATPG Throughput While Reducing Care Bits: Optimizing Transition Fault Patterns (Outstanding Technical Paper Award)
Author(s): Mudasir Kawoosa, Rajesh Mittal, Prakash Narayanan - Texas Instruments, Surya Samavedam - NVIDIA
PaperPresentation

WD1.3 User Paper: Sharing Scan-Ins For Similar Cores
Author(s): Deepak Agrawal, Daryl Pereira, Sanjay Shinde, Aanand Venkatachalam - LSI India
PaperPresentation

WD2: Synopsys User & Tutorial Session
WD2.2 User Paper: A Methodology of Automation of SoC Validation using FPGA
Author(s): Debabrata Ghosh, Felix Paul - Infineon Technologies
PaperPresentation

WD3: User and Tutorial Session
WD3.1 User Paper: Simplify Secure System Validation and Development: HAPS Prototyping Case Study
Author(s): Yuvaraj Ghorpade - LSI India
PaperPresentation

WD3.2 User Paper: Challenges in Mapping Multi-core A15 ARM Processor on FPGA (Outstanding Technical Paper Award)
Author(s): Doug Hogberg, Badri Seshadri - NVIDIA