SNUG Israel 2013 Proceedings

2014|2013|2012|2011|2010
Sort proceedings by:


Complete Proceedings


User Papers and Presentations
B1 - Tutorial and User Experience: Designing and Debugging with Verdi3
A New Automated Gate-Level Waveform from RTL Waveform Generation Methodology - Reduces Power Estimation Time from Weeks to Hours
Author(s): Ophir Turbovitch - CSR
Presentation

B2 - Tutorial and User Experience: Emulation and Congruency
Hardware Congruency - Introducing Hardware Semantics for RTL Simulations
Author(s):
PaperPresentation

B4 - User & Tutorial Session: Hierarchical Design, Multi-source Clock, ICC-2013.03 Update
Feed Through Insertion at Hierarchical Design Flow (Technical Committee Award)
Author(s): Gilad Konsker, Avi Zukerman - CSR
PaperPresentation

High-Speed Clock Tree Implementation Using “Multi Source CTS” Capabilities
Author(s):
PaperPresentation

C1 - Tips for using System Verilog (SV) Interface for Design
System Verilog (SV) Interfaces for RTL-Design
Author(s): Guy Nakibly - Annapurna Labs
PaperPresentation

C1 - Tips for Using System Verilog (SV) Interface for Design
Reducing Gate-Level Cycle Time Using VCS Advanced Features
Author(s): Ron M. Bar, Eran Glickman, Benny Michalovich, Erez Parnes - Freescale
PaperPresentation

Tuning VCS Compilation with Pre-compile IP Flow
Author(s): Arik Rachevsky - Synopsys
PaperPresentation

C3 - Low-Power Experience and DC Updates
Implementing UPF Flow for SoC Design (Best Paper Award)
Author(s):
PaperPresentation

C5 - Tutorial and User Experience: Design for Test
Use of Synopsys Inserted Scan Wrappers in SoC ATPG
Author(s): Eli Borowitz - Broadcom
PaperPresentation

Tutorials
A1 - Vision Session - Verification
Verification Continum
Author(s): Arturo Salz - Synopsys
Tutorial

A3 - From FinFETs to ECOs
Design with FinFET & Double-Patterning, a Brief History of the Future
Author(s): Marco Casalle-Rossi - Synopsys
Tutorial

New Technologies for Faster Implementation of Functional ECOs
Author(s): Mitch Mlinar - Synopsys
Tutorial

A5 - Custom Design – Overview and User Experience
Laker 3 Custom Layout System - "An Advanced Process Node Custom Layout Tutorial"
Author(s): Uri Golan - Synopsys
Tutorial

A6 - ARC Tutorial and User Experience:
Efficient High-Performance Processing
Author(s): Yankin Tanurhan - Synopsys

B1 - Tutorial and User Experience: Designing and Debugging with Verdi3
Verdi3 Transaction-based Debugging for SoC Designs
Author(s): Arnold Sher - Synopsys
Tutorial

B2 - Tutorial and User Experience: Emulation and Congruency
Transaction-level Verification with ZeBu-Server - What, When, How
Author(s): Jacob David - Synopsys
Tutorial

B3 - Tutorial: Static Timing Analysis - Signoff
PrimeTime - New, Faster Timing Closure Technologies
Author(s): Synopsys
Tutorial

B4 - User & Tutorial Session: Hierarchical Design, Multi-source Clock, ICC-2013.03 Update
ICC 2013.03 Release Update
Author(s): Synopsys
Tutorial

B5 - Tutorial: Advancing AMS Verification
Advanced AMS Verification and Techniques using Synopsys FastSPICE and Mixed-Signal Solutions
Author(s): Synopsys
Tutorial

B6 - Tutorial: Implementing 10G Backplane Systems
Achieving Predictable and Highly-Reliable 10G Backplane Designs
Author(s): Synopsys

C2 - Prototyping Tutorial
Synthesis Methods for FPGA-based Prototyping and HAPS-70 Family Overview
Author(s): Yair Dahan - Synopsys
Tutorial

C3 - Low-Power Experience and DC Updates
DC 2013.03 Release Update
Author(s): Gal Hason, Eyal Odiz - Synopsys
Tutorial

Introduction of Multi-Bit Banking Solution
Author(s): Sharon Avital - Synopsys
Tutorial

C4 - Tutorial: Implementation Flows for ARM Cores
Engineering Trade-Offs in the Implementation of a High-Performance Dual Core ARM® Cortex™-A15 Processor
Author(s): Joe Waltson, Moshe Ashkenazi, Erik Olson - Synopsys
Tutorial

C5 - Tutorial and User Experience: Design for Test
Meeting Test Quality Goals in Hierarchical Designs
Author(s): Adam Cron - Synopsys
Tutorial

C6 - Tutorials: Hardening DSP Cores and PCI Express IP
Hardening DSP Cores for Performance with DesignWare Logic Libraries and Embedded Memories
Author(s): Ran Snir, Ceva - Synopsys

In the Cloud With PCI Express
Author(s): Michael Chen - Synopsys