What is HSIC?

HSIC (High-Speed Inter-Chip) is an industry standard for USB chip-to-chip interconnect with a 2-signal (strobe, data) source synchronous serial interface using 240 MHz DDR signaling to provide only high-speed (480 Mbps data rate). No external cables or connectors and hot plug-n-play are supported. There is also no analog transceivers, and hence reduces the complexity, cost, power consumption, and manufacturing risk. Low power can be achieved with 1.2 V LVCMOS signaling levels instead of the 3.3 V signaling requirement. Both data and strobe are bi-directional utilizing NRZI encoding. In addition, HSIC interface is always operated at high speed, 480 Mbps. Hence, no high-speed chirp protocol is needed during enumeration. Finally, HSIC USB is fully compatible with existing USB software stacks and provides all data transfer needs through a single unified USB software stack. For more technical information regarding the requirements to implement a HSIC USB solution, please refer to the High-Speed Inter-Chip USB Electrical Specification, Version 1.0 (a supplement to the USB 2.0 specification.) which is now available online at http://www.usb.org/developers/docs/docs

Why HSIC?

HSIC replaces I2C
I2C isn’t fast enough and requires special drivers
HSIC allows USB Software reuse
PHY reuse/adaptation of existing PHY technologies

HSIC Device Using Synopsys USB 2.0 Device Controller and HSIC PHY

USB chip-to-chip interconnect can be achieved with the use of both Synopsys device controller and HSIC PHY. It eliminates USB cables and connector connection down to two wires for high speed chip-to-chip communication. It also allows low power high-speed data transfers (480 Mbps) using a source-synchronous serial interface. By eliminating the need of 3.3 V signaling and 5 V short protection logic, Synopsys HSIC PHY can offer approximately up to 50 percent lower power and 75 percent smaller area compared to traditional USB 2.0 PHYs.

USB 2.0 HSIC PHY

HSIC USB version 1.0 compliance
HSIC USB Features
- Supports 8/16-bit unidirectional parallel interfaces for HS mode of operation in accordance with the UTMI+ specification
- Implements data recovery from serial data on the HSIC connector
- Implements SYNC/End-of-Packet (EOP) generation and checking
- Implements bit stuffing and unstuffing, and bit-stuffing error detection
- Implements Non Return to Zero Invert (NRZI) encoding and decoding
- Implements bit serialization and deserialization
- Implements holding registers for staging transmit and receive data
- Implements logic to support suspend, sleep, resume, and remote wakeup operations
General Features
- Occupies small area
- Implements low power dissipation while active, idle, or on standby
- Implements one parallel data interface and clock for high-speed HSIC data transfers
- Provides parameter override bits for optimal yield and interoperability
- Provides on-chip PLL to reduce clock noise and eliminate the need for an external clock generator
- Provides Built-in Self-Test (BIST) circuitry to confirm high-speed operation
- Provides extensive test interface
Technical Specification
- Small area with approx. 0.18 sq. mm (macro + pads)
- Low power
  - HS transmit ~27 mW (typical)
  - HS receive ~18 mW (typical)
  - Suspend and sleep modes ~4uA
- Supports 12/24/48 MHz clock
- Initial process - TSMC 65LP
Compatability
- The HSIC PHY uses the same UTMI interface to communicate with Synopsys device controller. Since there is no well defined standard on the UTMI interface for HSIC and we have not tested the HSIC PHY with non-Synopsys device controllers yet, we do not guarantee that the UTMI interface of HSIC PHY would work well with that of non-Synopsys device controllers.
Availability
- Please contact Synopsys if you are interested in this feature for your USB product.

USB 2.0 Device Controller with HSIC feature

Configuration
- New device controller configuration option is available to enable HSIC support.
  - HSIC logic is implemented through an `ifdef statement. The logic will additionally be controlled by a strap pin.
- Device controller needs to be configured to support unidirectional UTMI PHY interface.
PHY interface specific
- No new pin is required to interface to Synopsys HSIC PHY for HSIC purposes. Unidirectional UTMI PHY interface is used.
- When the device controller is interfacing to Synopsys HSIC PHY, both the device controller and the PHY are of the understanding not to go through the chirp enumeration steps, but rather go to high-speed idle directly.
Application Interface/logic

New strap input pin from Application to enable/disable HSIC support (if the core is already configured to support HSIC through coreConsultant/RapidScript)
This new strap input pin will not be existed if the device controller is configured not to support HSIC.
Hardware impact

Device controller will bypass the Chirp enumeration stage in the chirp_gen_state state machine of udc20_speed_enum module if HSIC feature is supported.
The bypassing of the chirp enumeration stage will only happen if the associated strap signal is also enabled. If the strap signal is not yet enabled, the core will go through the normal chirp handshake mechanism to support non-HSIC PHY.
Firmware impact

No significant change is needed. Supporting high speed falling back to full speed mode is no longer needed when attaching to a HSIC USB host during enumeration because HSIC chip-to-chip interconnect supports high-speed operation only. Hence, a high-speed only device driver is needed.
Compatability

The device controller uses the same UTMI interface to communicate with Synopsys HSIC PHY. Since there is no well defined standard on the UTMI interface for HSIC and we have not tested the device controller with non-Synopsys HSIC PHYs yet, we do not guarantee that the UTMI interface of device controller would work well with that of non-Synopsys HSIC PHYs.
Availability

Please contact Synopsys if you are interested in this feature for your USB product.