The Synopsys DesignWare® DDR3/2 SDRAM Memory Controller IP (MCTL) offers an efficient digital interface between up to 32 on-chip application buses and a DDR3/2 physical layer (PHY) in a DDR3 or DDR2 memory subsystem servicing data rates up to 2133 Mbps. The MCTL is a full-featured memory controller that provides efficient DDR control and protocol translation, support for multiple application ports, quality of service (QoS) control and optimized memory transaction scheduling. The MCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data training.
DesignWare DDR3/2 IP Demo at 1600 Mbps Live from DesignCon 2010, see how the DesignWare DDR3/2 IP enables automatic timing compensation for voltage and temperature changes, per bit deskew adjustments in the datapath, and on-chip capabilities for measuring write and read data eyes.
Graham Allan Product Marketing Manager, Memory Interface IP