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The Synopsys USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low-power mobile and consumer applications such as next-generation handheld game machines, feature-rich smart phones, digital cameras and portable audio/video players. The Synopsys USB 2.0 nanoPHY IP delivers approximately half the power and area, compared to other solutions, for longer battery life and lower silicon cost. Designed for high yield, the Synopsys USB 2.0 nanoPHY implements architectural features that make it less sensitive to variations in foundry process, device models, package and board parasitics.
Highlights & Key Features
- Designed for advanced manufacturing processes, the USB 2.0 nanoPHY is targeted to leading 40nm, 45nm, 65nm, 90nm, and 130nm low power (LP) CMOS digital logic processes.
- Integrates high-speed mixed-signal, custom CMOS circuitry designed to the UTMI+ Level 3 Specification.
- Supports the USB 2.0 480-Mbps protocol and data rate (hi-speed).
- Backward compatible to the USB 1.1 legacy protocol at 1.5-Mbps (low-speed) and 12-Mbps (full-speed).
- Can be connected with a Hi-Speed and OTG subsystem to perform as a standard Hi-Speed, Dual-Role Device (DRD), operating as either a fully USB 2.0 Hi-Speed compliant peripheral or an OTG host.
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