Articles

Static Checks for Power Management at RTL
EDA DesignLine, Krishna Balachandran (Synopsys)
May 20, 2008

Voltage-aware simulation: No longer a fad, but a must for low-power designers
EDN, Krishna Balachandran (Synopsys)
May 14, 2008

Architectural Issues for Power Gating
Portable Design - Mike Keating, Alan Gibbons, Kaijian Shi (Synopsys), David Flynn and Robert Aiken (ARM)
April 8, 2008

Low Power Design For Analog/Mixed-Signal IP
EDA DesignLine - Navraj Nandra
March 4, 2008

Perform low power manufacturing test, part 1
EETimes-Asia, Chris Allsup
Jan 16-31, 2008

Perform low power manufacturing test, part 2
EETimes-Asia, Chris Allsup
February 1, 2008

Why Power Standards Matter
EETimes-Europe, Larry Vivolo
January 14 – February 3, 2008

Design Tools Now Embrace Power Consciousness
Power Systems Design Europe: Mary Ann White
Jan/Feb 2008

Low Power Methodology Manual for System-on-Chip Design
Electronic Design, Michael Keating, David Flynn, Rob Aitken, Alan Gibbons, and Kaijian Shi
January 7, 2008

Strengthening the Design System Through Interoperability
Chip Design Magazine
Oct/Nov 2007

Detecting Leakage Problems in Low-Power Designs
Nikkei Electronics Asia: Mike Demler
September 2007

Power-Sensitive 65nm Designs Increase the Need for Transistor-Level Verification
EDA DesignLine, Mike Demler
August 27, 2007

Analog and Mixed-signal Connectivity at 65nm and Below
EDA DesignLine, Navraj Nandra
May 7, 2007

Unified Power Format lowers power consumption in SOCs
EETimes, Mike Keating
February 12, 2007

Practical Power Network Synthesis of Power Gating Designs
EDA DesignLine, Kaijian Shi, Zhian Lin, Yi-Min Jiang
June 5, 2007

Practical Ways to Estimate, Implement and Verify SoC Decoupling Capacitance
Electronic Design, John Pedicone, and David Stringfellow
October 27, 2007

Trends in Wireless Consumer Electronics Drive the Need for More Complex Mixed-signal Devices
Chip Design Magazine, Mike Demler
November 2006